ADSP-21267 Datasheet, PDF (1/44 Pages) Analog Devices – Preliminary Technical Data

Preliminary Technical Data
SHARC^® Processor
ADSP-21267
SUMMARY
High performance 32-bit/40-bit floating point processor
optimized for high performance audio processing
Code compatible with all other SHARC DSPs
The ADSP-21267 processes high performance audio while
enabling low system costs
Audio decoders and post processor-algorithms support.
Non-volatile memory can be configured to contain a com-
bination of PCM 96 kHz, Dolby Digital, Dolby Digital EX2,
Dolby Pro Logic IIx, DTS 5.1, DTS ES Discrete 6.1, DTS-ES
Matrix 6.1, DTS Neo:6, MPEG2x BC (2 channel) and others.
See www.analog.com/SHARC for a complete list
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O —a parallel port, an SPI port, four serial
ports, a digital audio interface (DAI) and JTAG test port
DAI incorporates two precision clock generators (PCG), and
an input data port (IDP) that includes a parallel data acqui-
sition port (PDAP), and three programmable timers, all
under software control by the signal routing unit (SRU)
On-chip memory—1M Bit of on-chip SRAM and a dedicated
3M Bits of on-chip mask-programmable ROM
The ADSP-21267 is available with a 150 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on page 43
Figure 1. FUNCTIONAL BLOCK DIAGRAM
CORE P ROCE SSO R
TIM ER
INSTRUCTION
CACHE
32 X 48-BIT
DAG1
8X4 X3 2
DAG 2
8X 4X32
PROG RAM
SEQ UE NCE R
DUAL PORTED MEMORY
BLOCK 0
S RAM
0.5 MBI T
ROM
1.5 MBIT
ADDR
DATA
DUAL P ORT ED ME MORY
BLOCK 1
S RAM
0.5 MBIT
ROM
1.5 MBI T
ADDR
DATA
32
PM ADDRE SS BUS
32
DM ADDRESS BUS
P ROCE SSI NG
ELEME NT
(PE X)
PRO CE SSI NG
EL EM EN T
(PEY )
PX REGIS TER
64 P M DATA BUS
64 DM DATA BUS
DMA CONTROLLER
2 2 C HA N N ELS
4
S PI PORT (1)
6
JTAG TES T & EMULATIO N
S
SERIAL P ORTS (6)
20
SIG NAL
ROUTING
UNIT
INPUT
DATA P ORTS (8)
P ARALLEL DATA
ACQUIS ITION PO RT
PRE CI SION CLOCK
G ENERATO RS (2)
3
TI ME RS (3)
IO D
IOA
(32)
(1 8)
GPIO FLAG S/
4
IRQ /TIMEXP
I OP
REGIS TERS
(MEMO RY MAP PED)
CONTROL,
STATUS, &
DAT A BUFFERS
A D D RE SS/
16
D A TA B U S/ GP IO
3
CON TR OL/G PIO
PARALLEL
PORT
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
Rev. PrA
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