ADSP-21267 Datasheet, PDF (32/44 Pages) Analog Devices – Preliminary Technical Data

ADSP-21267
PRELIMINARY TECHNICAL DATA
Parallel Data Acquisition Port (PDAP)
The timing requirements for the PDAP are provided in
Table 27. PDAP is the parallel mode operation of channel 0 of
the IDP. For details on the operation of the IDP, see the IDP
chapter of the ADSP-2126x Hardware Reference Manual. Note
that the most significant 16 bits of external PDAP data can be
provided through either the parallel port AD[15:0] or the
DAI_P[20:5] pins. The remaining 4 bits can only be sourced
through DAI_P[4:1]. The timing below is valid at the
DAI_P[20:1] pins or at the AD[15:0] pins.
Table 27. Parallel Data Acquisition Port (PDAP)
Parameter
Timing Requirements
t_SPCLKEN
t_HPCLKEN
t_PDSD
t_PDHD
t_PDCLKW
t_PDCLK
PDAP_CLKEN Setup Before PDAP_CLK Sample Edge¹
PDAP_CLKEN Hold After PDAP_CLK Sample Edge¹
PDAP_DAT Setup Before SCLK PDAP_CLK Sample Edge¹
PDAP_DAT Hold After SCLK PDAP_CLK Sample Edge¹
Clock Width
Clock Period
Min
Max
Unit
2.5
ns
2.5
ns
2.5
ns
2.5
ns
7
ns
20
ns
Switching Characteristics
t_PDHLDD
Delay of PDAP Strobe After Last PDAP_CLK Capture Edge for a Word 2 x t_CCLK
ns
t_PDSTRB
PDAP Strobe Pulse Width
1 x t_CCLK – 1
ns
1 _{Source pins of DATA are ADDR[7:0], DATA[7:0], or DAI pins. Source pins for SCLK and FS are: 1) DAI pins, 2) CLKIN through PCG, or 3) DAI pins through PCG.}
DAI_P[20:1]
(PDAP_CLK)
DAI_P[20:1]
(PDAP_CLKEN)
DATA
DAI_P[20:1]
(PDAP_STROBE)
t_PDCLKW
SAMPLE EDGE
t_SPCLKEN
t_PDSD
t_HPCLKEN
t_PDHD
t_PDHLDD
Figure 24. PDAP Timing
t_PDSTRB
Rev. PrA | Page 32 of 44 | January 2004