ADSP-BF561 Datasheet, PDF (39/64 Pages) Analog Devices – Blackfin Embedded Symmetric Multi-Processor

ADSP-BF561
Timer Cycle Timing
Table 28 and Figure 25 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of f_SCLK/2 MHz.
Table 28. Timer Cycle Timing
Parameter
Min
Max
Unit
Timing Characteristics
t_WL Timer Pulse Width Input Low¹ (Measured in SCLK Cycles)
t_WH Timer Pulse Width Input High¹ (Measured in SCLK Cycles)
Switching Characteristic
t_HTO Timer Pulse Width Output² (Measured in SCLK Cycles)
1
1
1
(2³²â€“1)
SCLK
SCLK
SCLK
1 _{The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPIxCLK input pins in PWM output mode.}
2 _{The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (2}32_{–1) cycles.}
CLKOUT
TMRx
(PWM OUTPUT MODE)
t_HTO
TMRx
(WIDTH CAPTURE AND
EXTERNAL CLOCK MODES)
t_WL
t_WH
Figure 25. Timer PWM_OUT Cycle Timing
Rev. C | Page 39 of 64 | December 2007