ADSP-BF561 Datasheet, PDF (31/64 Pages) Analog Devices – Blackfin Embedded Symmetric Multi-Processor

PPIxCLK
POLC = 0
PPIxCLK
POLC = 1
POLS = 1
PPIxSYNC1
POLS = 0
POLS = 1
PPIxSYNC2
POLS = 0
PPIx_DATA
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
DATA
DRIVING/
FRAME
SYNC
SAMPLING
EDGE
t_SFSPE
t_HFSPE
t_HDTPE
t_DDTPE
Figure 18. PPI GP Tx Mode with External Frame Sync Timing (Bit 4 of PLL_CTL Set)
ADSP-BF561
Rev. C | Page 31 of 64 | December 2007