ADSP-BF561 Datasheet, PDF (1/64 Pages) Analog Devices – Blackfin Embedded Symmetric Multi-Processor

FEATURES
Dual symmetric 600 MHz high performance Blackfin cores
328K bytes of on-chip memory
(see Memory Architecture on Page 4)
Each Blackfin core includes
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.35 V core V_DD with on-chip voltage regulator
2.5 V and 3.3 V compliant I/O
256-ball CSP_BGA (2 sizes) and 297-ball PBGA
package options
PERIPHERALS
Dual 12-channel DMA controllers
(supporting 24 peripheral DMAs)
2 memory-to-memory DMAs
VOLTAGE
REGULATOR
IRQ CONTROL/
WATCHDOG
TIMER
JTAG TEST
EMULATION
Blackfin Embedded
Symmetric Multiprocessor
ADSP-BF561
2 internal memory-to-memory DMAs and 1 internal memory
DMA controller
12 general-purpose 32-bit timers/counters with PWM
capability
SPI-compatible port
UART with support for IrDA
Dual watchdog timers
Dual 32-bit core timers
48 programmable flags (GPIO)
On-chip phase-locked loop capable of 0.5× to 64× frequency
multiplication
2 parallel input/output peripheral interface units supporting
ITU-R 656 video and glueless interface to analog front end
ADCs
2 dual channel, full duplex synchronous serial ports support-
ing eight stereo I²S channels
IRQ CONTROL/
WATCHDOG
TIMER
B
B
UART
IrDA
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
L2 SRAM
128K BYTES
SPI
SPORT0
CORE SYSTEM/BUS INTERFACE
IMDMA
CONTROLLER
EAB
32
BOOT ROM
DMA
CONTROLLER1
DEB
DMA
CONTROLLER2
32
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI0
PPI1
DAB
16
PAB 16
Figure 1. Functional Block Diagram
SPORT1
GPIO
TIMERS
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. C
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