ADSP-21060CZ-160 Datasheet, PDF (39/64 Pages) Analog Devices – SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
Table 25. Link Port Service Request Interrupts:1u and 2u Speed Operations
Parameter
Min
Timing Requirements
t_SLCK
t_HLCK
LACK/LCLK Setup Before CLKIN Low¹ 10
LACK/LCLK Hold After CLKIN Low¹ 2
1 _{Only required for interrupt recognition in the current cycle.}
5V
Max
3.3 V
Min
Max
10
2
Unit
ns
ns
Link Ports —2 × CLK Speed Operation
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK:
Setup Skew = t_LCLKTWH min – t_DLDCH – t_SLDCL
Hold skew is the maximum delay that can be introduced in
LCLK relative to LDATA:
Hold Skew = t_LCLKTWL min – t_HLDCH – t_HLDCL
Calculations made directly from 2 speed specifications will
result in unrealistically small skew times because they include
multiple tester guardbands.
Note that link port transfers at 2× CLK speed at 40 MHz
(t_CK = 25 ns) may fail. However, 2× CLK speed link port trans-
fers at 33 MHz (t_CK = 30 ns) work as specified.
Table 26. Link Ports—Receive
5V
3.3 V
Parameter
Min
Max
Min
Max
Unit
Timing Requirements
t_SLDCL
Data Setup Before LCLK Low
t_HLDCL
Data Hold After LCLK Low
t_LCLKIW
t_LCLKRWL
LCLK Period (2u Operation)
LCLK Width Low¹
t_LCLKRWH
LCLK Width High²
Switching Characteristics
t_DLAHC
t_DLALC
LACK High Delay After CLKIN High³
LACK Low Delay After LCLK High⁴
2.5
2.25
t_CK/2
4.5
4.25
18 + DT/2
6
2.25
2.25
t_CK/2
5.25
4
28.5 + DT/2
16
18 + DT/2
6
ns
ns
ns
ns
ns
29.5 + DT/2 ns
16
ns
1 _{For ADSP-21060L, specification is 5 ns min.}
2 _{For ADSP-21062, specification is 4 ns min, for ADSP-21060LC, specification is 4.5 ns min.}
3 _{LACK goes low with tDLALC relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.}
4 _{For ADSP-21060L, specification is 6 ns min, 18 ns max. For ADSP-21060C, specification is 6 ns min, 16.5 ns max. For ADSP-21060LC, specification is 6 ns min, 18.5 ns max.}
Rev. F | Page 39 of 64 | March 2008