ADSP-21060CZ-160 Datasheet, PDF (18/64 Pages) Analog Devices – SHARC Processor

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC
ADSP-21060L/ADSP-21062L SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS (3.3 V)
A Grade
C Grade
K Grade
Parameter Description
Min Max
Min Max
Min Max
Unit
V_DD
T_CASE
V_IH1¹
V_IH2²
V_IL ^{1, 2}
Supply Voltage
3.15 3.45
3.15 3.45
3.15 3.45
V
Case Operating Temperature
–40 +85
–40 +100
–40 +85
qC
High Level Input Voltage @ V_DD = Max
2.0 V_DD + 0.5
2.0 V_DD + 0.5
2.0 V_DD + 0.5
V
High Level Input Voltage @ V_DD = Max
2.2 V_DD + 0.5
2.2 V_DD + 0.5
2.2 V_DD + 0.5
V
Low Level Input Voltage @ V_DD = Min
–0.5 +0.8
–0.5 +0.8
–0.5 +0.8
V
1 _{Applies to input and bidirectional pins: DATA47–0, ADDR31–0, RD, WR, SW, ACK, SBTS, IRQ2–0, FLAG3–0, HGB, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, CPA,}
TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1
2 _{Applies to input pins: CLKIN, RESET, TRST}
ELECTRICAL CHARACTERISTICS (3.3 V)
Parameter
Description
Test Conditions
Min Max Unit
V_OH^{1, 2}
V_OL^{1, 2}
I_IH^{3, 4}
I_IL³
I_ILP⁴
I_OZH^{5, 6, 7, 8}
I_OZL^{5, 9}
I_OZHP⁹
I_OZLC⁷
I_OZLA¹⁰
I_OZLAR⁸
I_OZLS⁶
C_IN^{11, 12}
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Low Level Input Current
Low Level Input Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Three-State Leakage Current
Input Capacitance
@ V_DD = Min, I_OH = –2.0 mA
@ V_DD = Min, I_OL = 4.0 mA
@ V_DD = Max, V_IN = V_DD Max
@ V_DD = Max, V_IN = 0 V
@ V_DD = Max, V_IN = 0 V
@ V_DD = Max, V_IN = V_DD Max
@ V_DD = Max, V_IN = 0 V
@ V_DD = Max, V_IN = V_DD Max
@ V_DD = Max, V_IN = 0 V
@ V_DD = Max, V_IN = 1.5 V
@ V_DD = Max, V_IN = 0 V
@ V_DD = Max, V_IN = 0 V
f_IN = 1 MHz, T_CASE = 25°C, V_IN = 2.5 V
2.4
V
0.4
V
10
μA
10
μA
150 μA
10
μA
10
μA
350 μA
1.5
mA
350 μA
4.2
mA
150 μA
4.7
pF
1 _{Applies to output and bidirectional pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, TIMEXP, HBG, REDY, DMAG1, DMAG2,}
BR6–1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.
2 _{See “Output Drive Currents” for typical drive current capabilities.}
3 _{Applies to input pins: ACK, SBTS, IRQ2–0, HBR, CS, DMAR1, DMAR2, ID2–0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.}
4 _{Applies to input pins with internal pull-ups: DR0, DR1, TRST, TMS, TDI.}
5 _{Applies to three-statable pins: DATA47–0, ADDR31–0, MS3–0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3–0, HBG, REDY, DMAG1, DMAG2, BMS, BR6–1, TFSx, RFSx,}
TDO, EMU. (Note that ACK is pulled up internally with 2 k: during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus
mastership.)
6 _{Applies to three-statable pins with internal pull-ups: DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.}
7 _{Applies to CPA pin.}
8 _{Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2 k: during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106xL}
is not requesting bus mastership).
9 _{Applies to three-statable pins with internal pull-downs: LxDAT3–0, LxCLK, LxACK.}
10_{Applies to ACK pin when keeper latch enabled.}
11_{Applies to all signal pins.}
12_{Guaranteed but not tested.}
Rev. F | Page 18 of 64 | March 2008