AD9525_13 Datasheet, PDF (39/48 Pages) Analog Devices – Low Jitter Clock Generator with Eight LVPECL Outputs

Data Sheet
AD9525
Table 36. Reserved
Reg.
Addr.
(Hex) Bits Bit Name
0x01B [7:0] Reserved
Description
Reserved.
0: default. All bits should be set to 0.
Table 37. PLL Block Power-Down
Reg.
Addr.
(Hex) Bits Name
Description
0x01C 7
N divider
ECL 2 CMOS
power-down
Turns off the N divider’s output clock. This stops the clock to the PFD and the frequency monitors.
0: clock on (default).
1: clock off.
6 N divider
power-down
N divider power-down.
0: N divider on (default).
1: N divider off.
5 REFB Divider
ECL 2 CMOS
power-down
This bit stops the clock to the frequency monitors for REFB. If this bit is disabled, the automatic reference
switchover does not operate. In some configurations, enabling the REFB divider ECL 2 CMOS may increase
reference spurs on clock outputs.
0: on.
1: off (default).
4 REFA Divider
ECL 2 CMOS
power-down
This bit stops the clock to the frequency monitors for REFA. If this bit is disabled, the automatic reference
switchover does not operate. In some configurations, enabling the REFA Divider ECL 2 CMOS may
increase reference spurs on clock outputs.
0: on (default).
1: off.
3 REFB divider
power-down
Powers down REFB divider. The REFB input receiver is still powered up.
0: REFB divider on (default).
1: REFB divider off.
2 REFA divider
power-down
Powers down REFA divider. The REFA input receiver is still powered up.
0: REFA divider on (default).
1: REFA divider off.
1
REFB channel
Powers down REFB channel. The REFB input receiver is powered down.
power-down
0: REFB channel on.
1: REFB channel off (default).
0
REFA channel
Powers down REFA channel. The REFA input receiver is powered down.
power-down
0: REFA channel on (default).
1: REFA channel off.
Rev. A | Page 39 of 48