AD9525_13 Datasheet, PDF (3/48 Pages) Analog Devices – Low Jitter Clock Generator with Eight LVPECL Outputs

Data Sheet
AD9525
SPECIFICATIONS
Typical is given for VDD3 = 3.3 V ± 5%; VDD3 ≤ VDD_CP ≤ 5.25 V; TA = 25°C; OUT_RSET resistor = 4.12 kΩ; CP_RSET resistor (CPRSET) =
5.1 kΩ, unless otherwise noted. Minimum and maximum values are given over full VDD3 and TA (−40°C to +85°C) variation as listed in Table 1.
REFA at 122.88 MHz, CLKIN frequency = 2949.12 MHz.
CONDITIONS
Table 1.
Parameter
SUPPLY VOLTAGE
VDD3
VDD_CP
OUT_RSET PIN RESISTOR
CP_RSET PIN RESISTOR (CPRSET RESISTOR)
TEMPERATURE RANGE, TA
Min Typ Max Unit
3.3
V
VDD3
5.25 V
4.12
kΩ
5.1
kΩ
−40 +25 +85 °C
Test Conditions/Comments
3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA
(CP_LSB = 600 µA); actual current calculated by
CP_LSB = 3.06/CPRSET, connect to ground; CPRSET
range = 2.7 kΩ to10 kΩ
SUPPLY CURRENT
Table 2.
Parameter
SUPPLY CURRENT FOR VDD3 and VDD_CP PINS
Min Typ Max Unit
VDD3 (Pin 3, Pin 36, Pin 41, Pin 46), Total Supply
Voltage for Outputs
VDD3 (Pin 9), Supply Voltage for M Divider,
CLK Inputs and Distribution
VDD_CP (Pin 13), Supply Voltage for Charge Pump
VDD3 (Pin 20), Supply Voltage for PLL
VDD3 (Pin 32), Supply Voltage for SYNC_OUT
310 369 mA
98 107 mA
6.6 7.6 mA
53 63.4 mA
45 54 mA
Test Conditions/Comments
fCLK = 2949.12 MHz; REFA and REFB enabled
at 122.88 MHz; R dividers = 2; M divider = 2;
PFD = 61.44 MHz; eight LVPECL outputs at
1474.56 MHz; LVPECL 780 mV mode
Outputs terminated with 50 Ω to VDD3 − 2 V
POWER DISSIPATION
Table 3.
Parameter
POWER DISSIPATION, CHIP
Power-On Default
Typical Operation 1
Typical Operation 2
PD Power-Down
PD Power-Down, Maximum Sleep
VDD_CP Supply
Min Typ Max Unit
782 871 mW
1.15 1.23 W
1.17 1.25 W
51 56.4 mW
13.2 19.1 mW
22 25 mW
Test Conditions/Comments
Does not include power dissipated in external
resistors; all LVPECL outputs terminated with
50 Ω to VDD3 − 2 V; LVPECL 780 mV mode
No programming; default register values
fCLK = 2949.12 MHz; REFA and REFB enabled
at 122.88 MHz; R dividers = 2; M divider = 2;
PFD = 61.44 MHz; eight LVPECL outputs at
1474.56 MHz
fCLK = 2949.12 MHz; PLL on; REFA enabled at
122.88 MHz; M divider = 1; PFD = 122.88MHz;
eight LVPECL outputs at 2949.12 MHz
PD pin pulled low
PD pin pulled low; power-down distribution
reference, Reg. 0x230[1] = 1b; note that powering
down distribution reference disables safe power-
down mode (see Power-Down Modes section)
PLL operating; typical closed-loop configuration
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