AD9525_13 Datasheet, PDF (37/48 Pages) Analog Devices – Low Jitter Clock Generator with Eight LVPECL Outputs

Data Sheet
AD9525
Table 33. REF_MON Pin Control
Reg.
Addr.
Bit
(Hex) Bits Name
Description
0x018 [7:5] Don’t
care
Don’t care.
[4:0] REF_MON Selects the signal that is connected to the REF_MON pin.
pin
control
Level or
Dynamic
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Signal Signal at REF_MON Pin
0
0
0
0
0
LVL
Ground (dc).
0
0
0
0
1
DYN
REFA clock.
0
0
0
1
0
DYN
REFB clock.
0
0
0
1
1
DYN
Selected reference clock to PLL.
0
0
1
0
0
DYN
Unselected reference clock to PLL.
0
0
1
0
1
LVL
Both reference clocks missing (active high).
0
0
1
1
0
LVL
Ground (dc).
0
0
1
1
1
LVL
Status REF A frequency (active high).
0
1
0
0
0
LVL
Status REF B frequency (active high).
0
1
0
0
1
LVL
(Status REF A frequency) AND (status REF B frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of feedback
clock).
0
1
0
1
1
LVL
Status of feedback clock (active high).
0
1
1
0
0
LVL
Selected reference (low: REFA, high: REFB).
0
1
1
0
1
LVL
DLD; active high.
0
1
1
1
0
LVL
N/A.
0
1
1
1
1
LVL
Ground, dc.
1
0
0
0
0
LVL
VDD3 (PLL power supply).
1
0
0
0
1
DYN
REFA.
1
0
0
1
0
DYN
REFB.
1
0
0
1
1
DYN
Selected reference to PLL.
1
0
1
0
0
DYN
Unselected reference to PLL.
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active low.
1
0
1
1
1
LVL
Status of REF A frequency (active low).
1
1
0
0
0
LVL
Status of REF B frequency (active low).
1
1
0
0
1
LVL
(Status of REFA frequency) AND (status of REFB frequency).
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of feedback clock).
1
1
0
1
1
LVL
Status of feedback clock (active low).
1
1
1
0
0
LVL
Selected reference (low: REFA, high: REFB); active low.
1
1
1
0
1
LVL
DLD (active low).
1
1
1
1
0
LVL
N/A.
1
1
1
1
1
LVL
VDD3 (PLL power supply).
Rev. A | Page 37 of 48