ADSP-TS202S_06 Datasheet, PDF (38/48 Pages) Analog Devices – TigerSHARC Embedded Processor

ADSP-TS202S
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by ΔV is
dependent on the capacitive load, C_L, and the drive current, I_D.
This ramp time can be approximated by the following equation:
t_RAMP = (C_LΔV) ⁄ I_D
The output enable time t_ENA is the difference between
t_{MEASURED_ENA} and t_RAMP as shown in Figure 35. The time
t_{MEASURED_ENA} is the interval from when the reference signal
switches to when the output voltage ramps ΔV from the mea-
sured three-stated output level. t_RAMP is calculated with test load
C_L, drive current I_D, and with ΔV equal to 0.4 V.
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see Figure 36). The delay and hold specifica-
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF. Figure 37
through Figure 44 show how output rise time varies with capac-
itance. Figure 45 graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see Output Disable Time on
Page 37.) The graphs of Figure 37 through Figure 45 may not be
linear outside the ranges shown.
TO
OUTPUT
PIN
50⍀
30pF
1.25V
Figure 36. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
STRENGTH 0
(V_{DD_IO} = 2.5V)
25
20
FALL TIME
15
Y = 0.251x + 4.2245
10
RISE TIME
Y = 0.259x + 3.0842
5
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
Figure 37. Typical Output Rise and Fall Time (10% to 90%, V_{DD_IO} = 2.5 V)
vs. Load Capacitance at Strength 0
STRENGTH 1
(V_{DD_IO} = 2.5V)
25
20
15
FALL TIME
Y = 0.1527x + 0.7485
10
5
RISE TIME
Y = 0.1501x + 0.05
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
Figure 38. Typical Output Rise and Fall Time (10% to 90%, V_{DD_IO} = 2.5 V)
vs. Load Capacitance at Strength 1
STRENGTH 2
(V_{DD_IO} = 2.5V)
25
20
15
FALL TIME
10
Y = 0.0949x + 0.8112
5
RISE TIME
Y = 0.0861x + 0.4712
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
Figure 39. Typical Output Rise and Fall Time (10% to 90%, V_{DD_IO} = 2.5 V)
vs. Load Capacitance at Strength 2
STRENGTH 3
(V_{DD_IO} = 2.5V)
25
20
15
FALL TIME
10
Y = 0.0691x + 1.1158
5
RISE TIME
Y = 0.06x + 1.1362
0
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (pF)
Figure 40. Typical Output Rise and Fall Time (10% to 90%, V_{DD_IO} = 2.5 V)
vs. Load Capacitance at Strength 3
Rev. C | Page 38 of 48 | December 2006