ADSP-TS202S_06 Datasheet, PDF (27/48 Pages) Analog Devices – TigerSHARC Embedded Processor

ADSP-TS202S
Table 27. Normal Reset Timing
Parameter
Timing Requirements
t_{RST_IN}
RST_IN Asserted
t_STRAP
RST_IN Deasserted After Strap Pins Stable
Switching Characteristic
t_{RST_OUT}
RST_OUT Deasserted After RST_IN Deasserted
RST_IN
RST_OUT
STRAP PINS
t_{RST_IN}
t_{RST_OUT}
t_{STRA P}
Min
Max
Unit
2
ms
1.5
ms
1.5
ms
Table 28. On-Chip DRAM Refresh¹
Figure 14. Normal Reset Timing
Parameter
Min
Max
Timing Requirement
t_REF
On-chip DRAM Refresh Period
1.56
1 _{For more information on setting the refresh rate for the on-chip DRAM, refer to the ADSP-TS201 TigerSHARC Processor Programming Reference.}
Unit
μs
Rev. C | Page 27 of 48 | December 2006