ADSP-TS202S_06 Datasheet, PDF (1/48 Pages) Analog Devices – TigerSHARC Embedded Processor

a
TigerSHARC^®
Embedded Processor
ADSP-TS202S
KEY FEATURES
500 MHz, 2.0 ns instruction cycle rate
12M bits of internal—on-chip—DRAM memory
25 mm × 25 mm (576-ball) thermally enhanced ball grid array
package
Dual-computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual-integer ALUs, providing data addressing and pointer
manipulation
Single-precision IEEE 32-bit and extended-precision 40-bit
floating-point data formats and 8-, 16-, 32-, and 64-bit
fixed-point data formats
Integrated I/O includes 14-channel DMA controller, external
port, four link ports, SDRAM controller, programmable
flag pins, two timers, and timer expired pin for system
integration
1149.1 IEEE-compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing
KEY BENEFITS
Provides high performance static superscalar DSP
operations, optimized for large, demanding multiproces-
sor DSP applications
Performs exceptionally well on DSP algorithm and I/O
benchmarks (see benchmarks in Table 1)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, host processors, and other (multiprocessor)
DSPs
Eases programming through extremely flexible instruction
set and high-level-language-friendly DSP architecture
Enables scalable multiprocessing systems with low
communications overhead
DATA ADDRESS GENERATION
INTEGER
32
32
INTEGER
J ALU
K ALU
PROGRAM
SEQUENCER
ADDR
FETCH
32-BIT × 32-BIT
J-BUS ADDR
J-BUS DATA
32-BIT × 32-BIT
BTB
K-BUS ADDR
K-BUS DATA
I-BUS ADDR
PC
I-BUS DATA
IAB
T
12M BITS INTERNAL MEMORY
MEMORY BLOCKS
(PAGE CACHE)
4 × CROSSBAR CONNECT
32 ^{A D A D A D A D}
128
32
128
32
SOC
I/F
128
S-BUS ADDR
21
S-BUS DATA 128
SHIFT
ALU MUL
128
X
REGISTER ₁₂₈
FILE
32-BIT × 32-BIT
DAB DAB
128
Y
128
REGISTER
FILE
MUL ALU SHIFT
32-BIT × 32-BIT
SOC BUS
JTAG PORT
6
JTAG
EXTERNAL
PORT
HOST
32
ADDR
MULTI-
PROC
64
DATA
SDRAM
CTRL
8
CTRL
C-BUS ¹⁰ _CTRL
ARB
EXT DMA
REQ 4
DMA
LINK PORTS
4
IN 8
L0
4
OUT 8
4
IN 8
L1
4
OUT 8
4
IN 8
L2
4
OUT 8
4
IN 8
L3
4
OUT 8
COMPUTATIONAL BLOCKS
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
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