ADSP-21991 Datasheet, PDF (35/44 Pages) Analog Devices – Mixed Signal DSP Co

ADSP-21991
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• Number of output pins that switch during each cycle (O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (V_DD)
and is calculated by the formula below.
P_EXT = O × C × V_DD² × f
Table 15. P_EXT Calculation Example
Pin Type
Address
MSx
WR
Data
CLKOUT
No. of Pins
15
1
1
16
1
% Switching
50
0
50
؋C
10 pF
10 pF
10 pF
10 pF
10 pF
The load capacitance includes the package capacitance (C_IN of
the processor). The switching frequency includes driving the load
high and then back low. Address and data pins can drive high and
low at a maximum rate of 1/(2t_CK). The write strobe can switch
every cycle at a frequency of 1/t_CK. Select pins switch at 1/(2t_CK),
but selects can switch on each cycle. For example, estimate P_EXT
with the following assumptions:
• A system with one bank of external data memory—asyn-
chronous RAM (16-bit)
• One 64K؋16 RAM chip is used with a load of 10 pF
• Maximum peripheral speed CCLK = 80 MHz, HCLK =
80 MHz
• External data memory writes occur every other cycle, a
rate of 1/(4t_HCLK), with 50% of the pins switching
• The bus cycle time is 80 MHz (t_HCLK = 12.5 ns)
The P_EXT equation is calculated for each class of pins that can
drive as shown in Table 15.
؋f
20 MHz
20 MHz
40 MHz
20 MHz
80 MHz
؋ V_DD2
10.9 V
10.9 V
10.9 V
10.9 V
10.9 V
= P_EXT
= 0.01635 W
= 0.0 W
= 0.00436 W
= 0.01744 W
= 0.00872 W
=0.04687 W
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation with the
following formula.
P_TOTAL= P_EXT + P_INT
Where:
• P_EXT is from Table 15
• P_INT is I_DDINT ؋ 2.5 V, using the calculation I_DDINT listed
in Power Dissipation.
Note that the conditions causing a worst-case P_EXT are different
from those causing a worst-case P_INT. Maximum P_INT cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching simultaneously.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ∆V is dependent on the capacitive load, C_L and the
load current, I_L. This decay time can be approximated by the
following equation.
t_DECAY
=
C_-----L---∆_----V_---
I_L
The output disable time t_DIS is the difference between t_MEASURED
and t_DECAY as shown in Figure 18. The time t_MEASURED is the
interval from when the reference signal switches to when the
output voltage decays ∆V from the measured output high or
output low voltage. The t_DECAY is calculated with test loads C_L and
I_L, and with ∆V equal to 0.5 V.
REFERENCE
SIGNAL
t_DIS
V_{OH (MEASURED)}
V_{OL (MEASURED)}
t_{M EASU RED}
t_ENA
V_{OH (MEASURED)} – ⌬V 2.0V
V_{OL (MEASURED)} + ⌬V 1.0V
t_DECAY
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS VOLTAGE
TO BE APPROXIMATELY 1.5V
Figure 18. Output Enable/Disable
REV. 0
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