ADSP-21991 Datasheet, PDF (28/44 Pages) Analog Devices – Mixed Signal DSP Co

ADSP-21991
External Port Bus Request/Grant Cycle Timing
Table 10 and Figure 11 describe external port bus request and
bus grant operations.
Table 10. External Port Bus Request and Grant Cycle Timing
Parameter^{1, 2}
Min
Timing Requirements
t_BS
BR Asserted to CLKOUT High Setup
4.6
t_BH
CLKOUT High to BR Deasserted Hold Time
0
Switching Characteristics
t_SD
CLKOUT High to xMS, Address, and RD/WR Disable
t_SE
CLKOUT Low to xMS, Address, and RD/WR Enable
0
t_DBG
CLKOUT High to BG Asserted Setup
0
t_EBG
CLKOUT High to BG Deasserted Hold Time
0
t_DBH
CLKOUT High to BGH Asserted Setup
0
t_EBH
CLKOUT High to BGH Deasserted Hold Time
0
1 _{tHCLK is the peripheral clock period.}
2 _{These are timing parameters that are based on worst-case operating conditions.}
Max
0.5t_HCLK +1
4
4
4
4
4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKOUT
BR
MS3--0
IOMS
BMS
A21–0
WR
RD
BG
BGH
t_BS
t_BH
t_SD
t_SD
t_SD
t_DBG
t_DBH
t_SE
t_SE
t_SE
t_EBG
t_EBH
Figure 11. External Port Bus Request and Grant Cycle Timing
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