ADSP-21991 Datasheet, PDF (23/44 Pages) Analog Devices – Mixed Signal DSP Co

ADSP-21991
Clock In and Clock Out Cycle Timing
Table 5 and Figure 6 describe clock and reset operations. Com-
binations of CLKIN and clock multipliers must not select
core/peripheral clocks in excess of 160 MHz/80 MHz for the
ADSP-21991BST and 150 MHz/75 MHz for the ADSP-
21991BBC, when the peripheral clock rate is one-half the core
clock rate. If the peripheral clock rate is equal to the core clock
rate, the maximum peripheral clock rate is 80 MHz for the
ADSP-21991BST and 75 MHz for the ADSP-21991BBC. The
peripheral clock is supplied to the CLKOUT pins.
When changing from bypass mode to PLL mode, allow 512
HCLK cycles for the PLL to stabilize.
Table 5. Clock In and Clock Out Cycle Timing
Parameter
Min
Timing Requirements
t_CK
CLKIN Period^{1, 2}
t_CKL
CLKIN Low Pulse
t_CKH
CLKIN High Pulse
t_WRST
t_MSS
t_MSH
RESET Asserted Pulsewidth Low
MSELx/BYPASS Stable Before RESET Deasserted Setup
MSELx/BYPASS Stable After RESET Deasserted Hold
t_MSD
MSELx/BYPASS Stable After RESET Asserted
t_PFD
Flag Output Disable Time After RESET Asserted
10
4.5
4.5
200t_CLKOUT
40
1000
Max
200
200
10
Unit
ns
ns
ns
ns
µs
ns
ns
ns
Switching Characteristics
t_CKOD
t_CKO
CLKOUT Delay from CLKIN
CLKOUT Period³
0
5.8
ns
12.5
ns
1 _{In clock multiplier mode and MSEL6–0 set for 1:1 (or CLKIN = CCLK), tCK = tCCLK.}
2 _{In bypass mode, tCK = tCCLK.}
3 _{CLKOUT jitter can be as great as 8 ns when CLKOUT frequency is less than 20 MHz. For frequencies greater than 20 MHz, jitter is less than 1 ns.}
CLKIN
RESET
MSEL6–0
BYPASS
DF
CLKOUT
t_CK
t_CKL
t_CKH
t_WRST
t_MSD
t_PFD
t_MSS
t_MSH
t_CKOD
t_CKO
Figure 6. Clock In and Clock Out Cycle Timing
REV. 0
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