ADSP-21160NCBZ-100 Datasheet, PDF (33/60 Pages) Analog Devices – SHARC Digital Signal Processor

Multiprocessor Bus Request and Host Bus Request
See Table 22 and Figure 19. Use these specifications for passing
of bus mastership between multiprocessing ADSP-21160x DSPs
(BRx) or a host processor, both synchronous and asynchronous
(HBR, HBG).
Table 22. Multiprocessor Bus Request and Host Bus Request
Parameter
Timing Requirements
t_HBGRCSV
t_SHBRI
t_HHBRI
t_SHBGI
t_HHBGI
t_SBRI
t_HBRI
t_SRPBAI
t_HRPBAI
HBG Low to RDx/WRx/CS Valid¹
HBR Setup Before CLKIN²
HBR Hold After CLKIN²
HBG Setup Before CLKIN
HBG Hold After CLKIN High
BRx, PA Setup Before CLKIN
BRx, PA Hold After CLKIN High
RPBA Setup Before CLKIN
RPBA Hold After CLKIN
Switching Characteristics
t_DHBGO
t_HHBGO
t_DBRO
t_HBRO
t_DPASO
t_TRPAS
t_DPAMO
t_PATR
t_DRDYCS
t_TRDYHG
t_ARDYTR
HBG Delay After CLKIN
HBG Hold After CLKIN³
BRx Delay After CLKIN
BRx Hold After CLKIN
PA Delay After CLKIN, Slave
PA Disable After CLKIN, Slave
PA Delay After CLKIN, Master
PA Disable Before CLKIN, Master⁴
REDY (O/D) or (A/D) Low from CS and HBR Low^{5, 6}
REDY (O/D) Disable or REDY (A/D) High from HBG^{5, 7}
REDY (A/D) Disable from CS or HBR High⁵
1 _{For ADSP-21160M, specification is 19 ns, maximum.}
2 _{Only required for recognition in the current cycle.}
3 _{For ADSP-21160M, specification is 2 ns, maximum.}
4 _{For ADSP-21160M, specification is 0.25tCK–5 ns, minimum.}
5 _{(O/D) = open drain, (A/D) = active drive.}
6 _{For ADSP-21160M, specification is 0.5tCK ns, maximum.}
7 _{For ADSP-21160M, specification is tCK+25 ns, maximum.}
ADSP-21160M/ADSP-21160N
Min
Max
Unit
6.5 + t_CK + t_CCLK – 12.5CR ns
6
ns
1
ns
6
ns
1
ns
9
ns
1
ns
6
ns
2
ns
7
ns
1.5
ns
8
ns
1.5
ns
8
ns
1.5
ns
0.25t_CCLK + 9
ns
0.25t_CCLK – 5.5
ns
0.5t_CK+1.0
ns
t_CK + 15
ns
11
ns
Rev. C | Page 33 of 60 | February 2013