ADSP-21160NCBZ-100 Datasheet, PDF (30/60 Pages) Analog Devices – SHARC Digital Signal Processor

ADSP-21160M/ADSP-21160N
Synchronous Read/Write—Bus Master
See Table 20 and Figure 17. Use these specifications for interfac-
ing to external memory systems that require CLKIN—relative
timing or for accessing a slave ADSP-21160x (in multiprocessor
memory space). These synchronous switching characteristics
are also valid during asynchronous memory reads and writes
except where noted (see Memory Read–Bus Master on page 26
and Memory Write–Bus Master on page 28).
When accessing a slave ADSP-21160x, these switching charac-
teristics must meet the slave’s timing requirements for
synchronous read/writes (see Synchronous Read/Write–Bus
Slave on page 32). The slave ADSP-21160x must also meet these
(bus master) timing requirements for data and acknowledge
setup and hold times.
Table 20. Synchronous Read/Write—Bus Master
Parameter
Timing Requirements
t_SSDATI
t_HSDATI
t_SACKC
t_HACKC
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Setup Before CLKIN
ACK Hold After CLKIN
Min
5.5
1
0.5t_CCLK + 3
1
Max
Unit
ns
ns
ns
ns
Switching Characteristics
t_DADDO
t_HADDO
t_DPGO
t_DRDO
t_DWRO
t_DRWL
t_DDATO
t_HDATO
t_DACKMO
t_ACKMTR
t_DCKOO
t_CKOP
t_CKWH
t_CKWL
Address, MSx, BMS, BRST, CIF Delay After CLKIN
Address, MSx, BMS, BRST, CIF Hold After CLKIN
PAGE Delay After CLKIN
RDx High Delay After CLKIN
WRx High Delay After CLKIN
RDx/WRx Low Delay After CLKIN
Data Delay After CLKIN¹
Data Hold After CLKIN
ACK Delay After CLKIN^{2, 3}
ACK Disable Before CLKIN²
CLKOUT Delay After CLKIN⁴
CLKOUT Period
CLKOUT Width High
CLKOUT Width Low
10
ns
1.5
ns
1.5
11
ns
0.25t_CCLK – 1
0.25t_CCLK+ 9
ns
0.25t_CCLK – 1
0.25t_CCLK + 9
ns
0.25t_CCLK – 1
0.25t_CCLK + 9
ns
0.25t_CCLK + 9
ns
1.5
ns
3
9
ns
–3
ns
0.5
5
ns
t_CK– 1
t_CK/2 – 2
t_CK/2 – 2
t_CK5 + 1
ns
t_CK/2 + 2²
ns
t_CK/2 + 2²
ns
1 _{For ADSP-21160M, specification is 12.5 ns, maximum.}
2 _{Applies to broadcast write, master precharge of ACK.}
3 _{For ADSP-21160M, specification is 0.25tCCLK+3 ns (minimum) and .25tCCLK+9 ns (maximum).}
4 _{For ADSP-21160M, specification is 2 ns, minimum.}
5 _{Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise. For more information, see the System Design chapter in the}
ADSP-21160 SHARC DSP Hardware Reference.
Rev. C | Page 30 of 60 | February 2013