ADSP-21160NCBZ-100 Datasheet, PDF (25/60 Pages) Analog Devices – SHARC Digital Signal Processor

ADSP-21160M/ADSP-21160N
Flags
For flags, see Table 17 and Figure 14.
Table 17. Flags
Parameter
Timing Requirements
t_SFI
t_HFI
t_DWRFI
t_HFIWR
FLAG3–0 IN Setup Before CLKIN High¹
FLAG3–0 IN Hold After CLKIN High¹
FLAG3–0 IN Delay After RDx/WRx Low^{1, 2}
FLAG3–0 IN Hold After RDx/WRx Deasserted¹
Min
Max
4
1
10
0
Switching Characteristics
t_DFO
t_HFO
t_DFOE
t_DFOD
FLAG3–0 OUT Delay After CLKIN High
FLAG3–0 OUT Hold After CLKIN High
CLKIN High to FLAG3–0 OUT Enable
CLKIN High to FLAG3–0 OUT Disable³
9
1
1
t_CK– t_CCLK + 5
1 _{Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.}
2 _{For ADSP-21160M, specification is 12 ns, maximum.}
3 _{For ADSP-21160M, specification is 5 ns, maximum.}
Unit
ns
ns
ns
ns
ns
ns
ns
ns
CLKIN
FLAG3–0 _OUT
CLKIN
FLAG3–0 _IN
RDx
WRx
t_DFOE
t_DFO
t_HFO
t_DFO
FLAG OUTPUT
t_SFI
t_DWRFI
FLAG INPUT
t_HFI
t_HFIWR
Figure 14. Flags
t_DFOD
Rev. C | Page 25 of 60 | February 2013