ADSP-21062 Datasheet, PDF (33/48 Pages) Analog Devices – ADSP-2106x SHARC DSP Microcomputer Family

ADSP-21062/ADSP-21062L
Link Ports: 1 ؋ CLK Speed Operation
Parameter
Receive
Timing Requirements:
t_SLDCL
t_HLDCL
t_LCLKIW
t_LCLKRWL
t_LCLKRWH
Data Setup Before LCLK Low
Data Hold After LCLK Low
LCLK Period (1 × Operation)
LCLK Width Low
LCLK Width High
ADSP-21062
Min
Max
3
3
t_CK
6
5
ADSP-21062L
Min
Max
3
3
t_CK
6
5
Units
ns
ns
ns
ns
ns
Switching Characteristics:
t_DLAHC
t_DLALC
t_ENDLK
LACK High Delay After CLKIN High
LACK Low Delay After LCLK High¹
LACK Enable from CLKIN
t_TDLK
LACK Disable from CLKIN
18 + DT/2
–3
5 + DT/2
28.5 + DT/2
13
20 + DT/2
18 + DT/2
–3
5 + DT/2
28.5 + DT/2 ns
13
ns
ns
20 + DT/2 ns
Transmit
Timing Requirements:
t_SLACH
LACK Setup Before LCLK High
18
18
ns
t_HLACH LACK Hold After LCLK High
–7
–7
ns
Switching Characteristics:
t_DLCLK LCLK Delay After CLKIN (1 × operation)
t_DLDCH Data Delay After LCLK High
t_HLDCH Data Hold After LCLK High
t_LCLKTWL LCLK Width Low
t_LCLKTWH LCLK Width High
t_DLACLK LCLK Low Delay After LACK High
t_ENDLK LDAT, LCLK Enable After CLKIN
t_TDLK
LDAT, LCLK Disable After CLKIN
–3
(t_CK/2) – 1
(t_CK/2) – 1.25
(t_CK/2) + 8.75
5 + DT/2
15.5
2.5
–3
(t_CK/2) + 1.25 (t_CK/2) – 1
(t_CK/2) + 1
(t_CK/2) – 1.5
(3 × t_CK/2) + 17 (t_CK/2) + 8
5 + DT/2
20 + DT/2
15.5
ns
2.5
ns
ns
(t_CK/2) + 1.5 ns
(t_CK/2) + 1
ns
(3 × t_CK/2) + 17 ns
ns
20 + DT/2 ns
Link Port Service Request Interrupts: 1 × and
2 × Speed Operations
Timing Requirements:
t_SLCK
LACK/LCLK Setup Before CLKIN Low² 10
10
ns
t_HLCK
LACK/LCLK Hold After CLKIN Low² 2
2
ns
NOTES
1_{LACK will go low with tDLALC relative to rising edge of LCLK after first nibble is received. LACK will not go low if the receiver’s link buffer is not about to fill.}
2_{Only required for interrupt recognition in the current cycle.}
REV. C
–33–