ADSP-21062 Datasheet, PDF (28/48 Pages) Analog Devices – ADSP-2106x SHARC DSP Microcomputer Family

ADSP-21062/ADSP-21062L
Asynchronous Read/Write—Host to ADSP-21062
Use these specifications for asynchronous host processor accesses
of an ADSP-21062, after the host has asserted CS and HBR
(low). After HBG is returned by the ADSP-21062, the host can
drive the RD and WR pins to access the ADSP-21062’s internal
memory or IOP registers. HBR and HBG are assumed low for
this timing.
Parameter
Read Cycle
Timing Requirements:
t_SADRDL
t_HADRDH
t_WRWH
t_DRDHRDY
t_DRDHRDY
Address Setup/CS Low Before RD Low¹
Address Hold/CS Hold Low After RD
RD/WR High Width
RD High Delay After REDY (O/D) Disable
RD High Delay After REDY (A/D) Disable
ADSP-21062
Min
Max
0
0
6
0
0
ADSP-21062L
Min
Max
0
0
6
0
0
Units
ns
ns
ns
ns
ns
Switching Characteristics:
t_SDATRDY
t_DRDYRDL
Data Valid Before REDY Disable from Low
2
REDY (O/D) or (A/D) Low Delay After RD Low
2
10
ns
10
ns
t_RDYPRD
REDY (O/D) or (A/D) Low Pulse
Width for Read
45 + 21DT/16
45 + 21DT/16
ns
t_HDARWH
Data Disable After RD High
2
8
2
8
ns
Write Cycle
Timing Requirements:
t_SCSWRL
CS Low Setup Before WR low
0
0
ns
t_HCSWRH
CS Low Hold After WR high
0
0
ns
t_SADWRH
Address Setup Before WR High
5
5
ns
t_HADWRH
Address Hold After WR High
2
2
ns
t_WWRL
WR Low Width
7
7
ns
t_WRWH
RD/WR High Width
6
6
ns
t_DWRHRDY WR High Delay After REDY
(O/D) or (A/D) Disable
0
0
ns
t_SDATWH
Data Setup Before WR High
5
5
ns
t_HDATWH
Data Hold After WR High
1
1
ns
Switching Characteristics:
t_DRDYWRL
REDY (O/D) or (A/D) Low Delay
After WR/CS Low
t_RDYPWR
REDY (O/D) or (A/D) Low Pulse
Width for Write
t_SRDYCK
REDY (O/D) or (A/D) Disable to CLKIN
10
10
ns
15 + 7DT/16
15 + 7DT/16
ns
1 + 7DT/16 8 + 7DT/16 1 + 7DT/16 8 + 7DT/16 ns
NOTE
1_{Not required if RD and address are valid tHBGRCSV after HBG goes low. For first access after HBR asserted, ADDR31-0 must be a non-MMS value 1/2 tCLK before RD}
or WR goes low or by t_HBGRCSV after HBG goes low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Proces-
sor Control of the ADSP-21062” section in the ADSP-21062 SHARC User’s Manual, Second Edition.
CLKIN
REDY (O/D)
t_SRDYCK
REDY (A/D)
O/D = OPEN DRAIN, A/D = ACTIVE DRIVE
Figure 18a. Synchronous REDY Timing
–28–
REV. C