ADSP-21062 Datasheet, PDF (21/48 Pages) Analog Devices – ADSP-2106x SHARC DSP Microcomputer Family

Memory Write—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
ADSP-21062/ADSP-21062L
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Parameter
Timing Requirements:
t_DAAK
t_DSAK
ACK Delay from Address, Selects^{1, 2}
ACK Delay from WR Low¹
ADSP-21062
Min
Max
ADSP-21062L
Min
Max
Units
14 + 7DT/8 + W
8 + DT/2 + W
14 + 7DT/8 + W ns
8 + DT/2 + W ns
Switching Characteristics:
t_DAWH Address, Selects to WR Deasserted²
t_DAWL Address, Selects to WR Low²
t_WW
WR Pulsewidth
t_DDWH Data Setup Before WR High
t_DWHA Address Hold After WR Deasserted
t_DATRWH Data Disable After WR Deasserted³
t_WWR WR High to WR, RD, DMAGx Low
t_DDWR Data Disable Before WR or RD Low
t_WDE WR Low to Data Enabled
t_SADADC Address, Selects to ADRCLK High²
17 + 15DT/16 + W
3 + 3DT/8
12 + 9DT/16 + W
7 + DT/2 + W
0.5 + DT/16 + H
1 + DT/16 + H
8 + 7DT/16 + H
5 + 3DT/8 + I
–1 + DT/16
0 + DT/4
6 + DT/16 + H
17 + 15DT/16 + W
ns
3 + 3DT/8
ns
12 + 9DT/16 + W
ns
7 + DT/2 + W
ns
0.5 + DT/16 + H
ns
1 + DT/16 + H 6 + DT/16 + H ns
8 + 7DT/16 + H
ns
5 + 3DT/8 + I
ns
–1 + DT/16
ns
0 + DT/4
ns
W = (number of wait states specified in WAIT register) × t_CK.
H = t_CK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = t_CK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTES
1_{ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-}
tion of ACK (High).
2_{The falling edge of MSx, SW, BMS is referenced.}
3_{See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.}
ADDRESS
MSx , SW
BMS
WR
DATA
ACK
t_DAWL
t_DAWH
t_WW
t_WDE
t_DAAK
t_DSAK
t_DDWH
t_DWHA
t_DATRWH
t_WWR
t_DDWR
RD , DMAG
ADRCLK
(OUT)
t_SADADC
Figure 14. Memory Write—Bus Master
REV. C
–21–