ADSP-BF535_15 Datasheet, PDF (32/44 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF535
Serial Peripheral Interface (SPI) Port
—Master Timing
Table 23 and Figure 15 describe SPI port master operations.
Table 23. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
t_SSPID
Data Input Valid to SCK Edge (Data Input Setup)
t_HSPID
SCK Sampling Edge to Data Input Invalid
Switching Characteristics
t_SDSCIM
SPIxSEL Low to First SCK Edge (x=0 or 1)
t_SPICHM
Serial Clock High Period
t_SPICLM
Serial Clock Low Period
t_SPICLK
t_HDSM
Serial Clock Period
Last SCK Edge to SPIxSEL High (x=0 or 1)
t_SPITDM
Sequential Transfer Delay
t_DDSPID
SCK Edge to Data Out Valid (Data Out Delay)
t_HDSPID
SCK Edge to Data Out Invalid (Data Out Hold)
Min
Max
6.5
1.6
(2 ؋ t_SCLK) – 3
(2 ؋ t_SCLK) – 3
(2 ؋ t_SCLK) – 3
4 ؋ t_SCLK
(2 ؋ t_SCLK) – 3
2 ؋ t_SCLK
0.0
6.0
0.0
5.0
SPIxSEL
(OUTPUT)
(x = 0 OR 1)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
t_{SD SCIM} t_{SPICH M}
t_{S P IC LM}
t_SPICLM
t_{SPICH M}
t_DDSPID
MOSI
(OUTPUT)
CPHA = 1
t_SSPID
MSB
t_HSPID
MISO
(INPUT)
MSB
VALID
t_DDSPID
MOSI
(OUTPUT)
CPHA = 0
t_SSPID
MISO
(INPUT)
MSB
MSB
VALID
t_HSPID
t_SPICLK
t_HDSM
t_SPITDM
t_{H D S P ID}
t_SSPID
LSB
LSB
VALID
t_{H S P I D}
t_HDSPID
LSB
LSB
VALID
Figure 15. Serial Peripheral Interface (SPI) Port—Master Timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–32–
REV. A