ADSP-BF535_15 Datasheet, PDF (28/44 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF535
Asynchronous Memory Read Cycle Timing
Table 15 and Figure 12 describe Asynchronous Memory Read
Cycle timing.
Table 15. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
t_SDAT
DATA31–0 Setup Before CLKOUT
t_HDAT
DATA31–0 Hold After CLKOUT
t_SARDY
t_HARDY
ARDY Setup Before CLKOUT
ARDY Hold After CLKOUT
Switching Characteristics
t_DO
Output Delay After CLKOUT¹
t_HO
Output Hold After CLKOUT ¹
1 _{Output pins include AMS3–0, ABE3–0, ADDR25–2, AOE, ARE.}
CLKOUT
AMSx
SETUP
2 CYCLES
t_DO
PROGRAMMED READ ACCESS
4 CYCLES
Min
Max
Unit
2.1
ns
2.6
ns
4.0
ns
–1.0
ns
7.0
ns
0.8
ns
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t_HO
ABE3–0
ADDR25–2
AOE
ARE
ARDY
DATA31–0
BE, ADDRESS
t_DO
t_SARDY
t_HARDY
t_HO
t_HARDY
t_SARDY
t_SDAT
READ
Figure 12. Asynchronous Memory Read Cycle Timing
t_HDAT
–28–
REV. A