AD9627-11_15 Datasheet, PDF (32/72 Pages) Analog Devices – 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

AD9627-11
Increment Gain (IG) and Decrement Gain (DG)
This comparison is subject to the ADC clock latency but allows
The increment gain and decrement gain indicators are intended
to be used together to provide information to enable external
a finer, more accurate comparison. The fine upper threshold
magnitude is defined by the following equation:
gain control. The decrement gain indicator works in
dBFS = 20 log(Threshold Magnitude/2¹³)
conjunction with the coarse upper threshold bits, asserting when
The decrement gain output works from the ADC fast detect
the input magnitude is greater than the 3-bit value in the coarse
output pins, providing a fast indication of potential overrange
upper threshold register (Address 0x105). The increment gain
conditions. The increment gain uses the comparison at the
indicator, similarly, corresponds to the fine lower threshold bits,
output of the ADC, requiring the input magnitude to remain
except that it is asserted only if the input magnitude is less than
below an accurate, programmable level for a predefined period
the value programmed in the fine lower threshold register after
before signaling external circuitry to increase the gain.
the dwell time elapses. The dwell time is set by the 16-bit dwell
time value located at Address 0x10A and Address 0x10B and is
set in units of ADC input clock cycles ranging from 1 to 65,535.
The fine lower threshold register is a 13-bit register that is
E ^{compared with the magnitude at the output of the ADC.}
The operation of the increment gain output and the decrement
gain output is shown in Figure 65.
UPPER THRESHOLD (COARSE OR FINE)
T _{DWELL TIME}
E _{TIMER RESET BY}
RISE ABOVE F_LT
FINE LOWER THRESHOLD
L _{C_UT OR F_UT*}
O ^F_LT
DG
IG
DWELL TIME
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE F_LT
S *C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.
NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.
OB^{Figure 65. Threshold Settings for C_UT, F_UT, IG, DG, and F_LT}
Rev. B | Page 32 of 72