AD9627-11_15 Datasheet, PDF (1/72 Pages) Analog Devices – 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

11-Bit, 105 MSPS/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9627-11
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SNR = 65.8 dBc (66.8 dBFS) to 70 MHz @ 105 MSPS
SFDR = 85 dBc to 70 MHz @ 105 MSPS
SDIO/ SCLK/
AVDD DVDD FD(0:3)A DCS DFS CSB DRVDD
Low power: 600 mW @ 105 MSPS
SNR = 65.7 dBc (66.7 dBFS) to 70 MHz @ 150 MSPS
FD BITS/THRESHOLD
SPI
DETECT
D10A
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
E ^{IF sampling frequencies to 450 MHz}
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
T _{Differential analog inputs with 650 MHz bandwidth}
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
E ^{Serial port control}
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
L _{Fast detect/threshold bits}
Composite signal monitor
APPLICATIONS
O _{Communications}
Diversity radio systems
Multimode digital receivers (3G)
S ^{GSM, EDGE, WCDMA, CDMA2000,}
WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
B ^{General-purpose software radios}
O ^{Broadband data applications}
VIN+A
VIN–A
VREF
SENSE
CML
RBIAS
SHA
REF
SELECT
ADC
PROGRAMMING DATA
SIGNAL
MONITOR
DIVIDE
1 TO 8
DUTY CYCLE
STABILIZER
DCO
GENERATION
VIN–B
VIN+B
SHA
ADC
AD9627-11
SIGNAL MONITOR
DATA
MULTICHIP FD BITS/THRESHOLD SIGNAL MONITOR
SYNC
DETECT
INTERFACE
D0A
CLK+
CLK–
DCOA
DCOB
D10B
D0B
AGND SYNC
FD(0:3)B
SMI SMI SMI DRGND
SDFS SCLK/ SDO/
NOTES
PDWN OEB
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1. Integrated dual, 11-bit, 105 MSPS/150 MSPS ADC.
2. Fast overrange detect and signal monitor with serial output.
3. Signal monitor block with dedicated serial output mode.
4. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
5. Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
6. Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
7. Pin compatibility with the AD9640, AD9627, and AD9600
for a simple migration from 11 bits to 14 bits, 12 bits, or
10 bits.
Rev. B
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