AD9627-11_15 Datasheet, PDF (10/72 Pages) Analog Devices – 11-Bit, 105 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter

AD9627-11
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
0.24
ns
0.40
ns
tDS
Setup time between the data and the rising edge of SCLK
2
ns
tDH
Hold time between the data and the rising edge of SCLK
2
ns
tCLK
Period of the SCLK
40
ns
tS
Setup time between CSB and SCLK
2
tH
Hold time between CSB and SCLK
2
tHIGH
SCLK pulse width high
10
tLOW
SCLK pulse width low
10
E ^tEN_SDIO
Time required for the SDIO pin to switch from an input to an
10
output relative to the SCLK falling edge
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
10
input relative to the SCLK rising edge
SPORT TIMING REQUIREMENTS
T _tCSSCLK
Delay from rising edge of CLK+ to rising edge of SMI SCLK
3.2
4.5
6.2
tSSCLKSDO
Delay from rising edge of SMI SCLK to SMI SDO
−0.4
0
0.4
tSSCLKSDFS
Delay from rising edge of SMI SCLK to SMI SDFS
−0.4
0
0.4
E _{Timing Diagrams}
OL _CLK+
CLK–
S _{CH A/CH B DATA}
N+1 ^N+2
N
t_A
t_CLK
N+3
N+4
N+ 5
N+ 6
N+ 7
N+ 8
t_PD
N – 13 N – 12
N – 11 N – 10
N–9
N–8
N–7
N–6
N–5 N–4
CH A/CH B FAST
DETECT
B _DCOA/DCOB
N–3
t_S
N–2
N–1
t_H
N
N+1
N+2
N+3
N+4
N+5 N+6
t_DCO
t_CLK
O^{Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)}
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. B | Page 10 of 72