ADSP-BF539_08 Datasheet, PDF (31/60 Pages) Analog Devices – Blackfin Embedded Processor

ADSP-BF539/ADSP-BF539F
Asynchronous Memory Read Cycle Timing
Table 17 and Table 18 on Page 32 and Figure 12 and Figure 13
on Page 32 describe asynchronous memory read cycle opera-
tions for synchronous and for asynchronous ARDY.
Table 17. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Timing Requirements
t_SDAT
t_HDAT
t_SARDY
t_HARDY
t_DO
t_HO
DATA15–0 Setup Before CLKOUT
DATA15–0 Hold After CLKOUT
ARDY Setup Before the Falling Edge of CLKOUT
ARDY Hold After the Falling Edge of CLKOUT
Output Delay After CLKOUT¹
Output Hold After CLKOUT¹
1 _{Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.}
Min
Max
2.1
0.8
4.0
0.0
6.0
0.8
CLKOUT
AMSx
SETUP
2 CYCLES
t_DO
PROGRAMMED READ ACCESS
4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
Unit
ns
ns
ns
ns
ns
ns
t_HO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA15–0
BE, ADDRESS
t_DO
t_HO
t_SARDY
t_HARDY
t_HARDY
t_SARDY
t_SDAT
READ
Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
t_HDAT
Rev. A | Page 31 of 60 | February 2008