AD9681 Datasheet, PDF (31/40 Pages) Analog Devices – Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

Data Sheet
AD9681
MEMORY MAP
The AD9681 uses a 3-wire (bidirectional SDIO) interface and 16-bit addressing. Therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0,
and Bit 3 and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset where all of the user registers revert to
their default values and Bit 2 is automatically cleared.
Table 17. Memory Map Register Table
Reg.
Addr.
(Hex)
Register Name
Bit 7
(MSB)
Bit 6
Chip Configuration Registers
0x00
SPI port
configuration
0=
SDIO
active
LSB first
Bit 5
Soft
reset
Bit 4
Bit 3
Bit 2
1=
16-bit
address
1=
16-bit
address
Soft
reset
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
LSB first
0 = SDIO 0x18
active
0x01 Chip ID (global)
0x02 Chip grade (global) Open
8-bit chip ID, Bits[7:0];
0x8F = the AD9681, an octal, 14-bit, 125 MSPS serial LVDS
Speed grade ID, Bits[6:4];
110 = 125 MSPS
Open
Open
Open
0x8F
Open
Read
only
Device Index and Transfer Registers
0x05 Device index
Open
Open
DCO±1, FCO±1, D1, D2
C1, C2
B1, B2
A1, A2 0x3F
DCO±2 FCO±2
data
data
data
data
clock
clock
channels channels channels channels
channels channels
0xFF Transfer
Open Open
Global ADC Function Registers
0x08
Power modes
(global)
Open
Open
0x09 Clock (global)
Open Open
0x0B
Clock divide
(global)
Open Open
Open
Open
Open
Open
Open
Initiate 0x00
override
External
power-
down
pin
function;
0 = full
power-
down,
1=
standby
Open
Open
Open
Open
Open
Open
Open
Open
Open
Internal power-down
mode, Bits[1:0];
00 = chip run
01 = full power-down
10 = standby
11 = digital reset
0x00
Open
Open
Duty
cycle
stabilizer;
0 = off
1 = on
Clock divide ratio, Bits[2:0];
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
0x01
0x00
Comments
Nibbles are
mirrored such
that a given
register value
yields the same
function for
either LSB-first
mode or MSB-
first mode.
The default
for ADCs is
16-bit mode.
Unique chip ID
used to differ-
entiate devices.
Read only.
Unique speed
grade ID used
to differentiate
graded devices.
Read only.
Bits are set to
determine
which device
on chip
receives the
next write
command.
The default is
all devices on
chip.
Sets resolution/
sample rate
override.
Determines
various generic
modes of chip
operation.
Turns duty
cycle stabilizer
on or off.
Divide ratio
is the value
plus 1.
Rev. A | Page 31 of 40