AD9681 Datasheet, PDF (24/40 Pages) Analog Devices – Octal, 14-Bit, 125 MSPS, Serial LVDS, 1.8 V Analog-to-Digital Converter

AD9681
DIGITAL OUTPUTS AND TIMING
The AD9681 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option (similar to the IEEE 1596.3 standard) via the
SPI. The LVDS driver current is derived on chip and sets the
output current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing (or 700 mV p-p
differential) at the receiver.
When operating in reduced range mode, the output current
reduces to 2 mA. This results in a 200 mV swing (or 400 mV p-p
differential) across a 100 Ω termination at the receiver.
The AD9681 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
placed as near to the receiver as possible. If there is no far end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is recom-
mended that the trace length be less than 24 inches, with all
traces the same length. Place the differential output traces as near
to each other as possible. An example of the FCO and data stream
with proper trace length and position is shown in Figure 49.
Figure 50 shows an LVDS output timing example in reduced
range mode.
Data Sheet
D0 500mV/DIV
D1 500mV/DIV
DCO 500mV/DIV
FCO 500mV/DIV
4ns/DIV
Figure 49. LVDS Output Timing Example in ANSI-644 Mode (Default)
D0 400mV/DIV
D1 400mV/DIV
DCO 400mV/DIV
FCO 400mV/DIV
4ns/DIV
Figure 50. LVDS Output Timing Example in Reduced Range Mode
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