AD9925 Datasheet, PDF (27/96 Pages) Analog Devices – CCD Signal Processor with Vertical Driver and Precision Timing Generator

Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10 ver-
tical pattern groups and adding repeats, the start position, and
horizontal clamping and blanking information. Up to 10 verti-
cal sequences may be programmed, each using the registers
shown in Table 14. Figure 36 shows how the different registers
are used to generate each vertical sequence.
The VPATSEL register selects which vertical pattern group will
be used in a given vertical sequence. The basic vertical pattern
group can have repetitions added for high speed line shifts or
line binning by using the VPATREPO and VPATREPE registers.
Generally, the same number of repetitions is programmed into
both registers, but if a different number of repetitions is re-
quired on odd and even lines, separate values may be used for
each register (see the Generating Line Alternation for Vertical
Sequence and HBLK section). The VPATSTART register speci-
fies the pixel location where the vertical pattern group will start.
The VMASK register is used in conjunction with the FREEZE/
RESUME registers to enable optional masking of the vertical
outputs. Either or both of the FREEZE1/RESUME1 and
FREEZE2/RESUME2 registers can be enabled using the
VMASK register.
AD9925
The line length (in pixels) is programmable using the HDLEN
registers. Each vertical sequence can have a different line length
to accommodate the various image readout techniques. The
maximum number of pixels per line is 8192. Note that the 13^th bit
(MSB) of the line length is located in a separate register. Also
note that the last line of the field is separately programmable
using the HDLAST register, located in the field register section.
Additional vertical sequences are provided in Register Bank 3
for the XV7 and XV8 outputs. This allows the AD9925 to re-
main backward-compatible with the AD9995 register settings
while still providing additional flexibility with XV7 and XV8 for
new CCDs.
As described in the Hold Area Using FREEZE/RESUME Regis-
ters section, the hold registers in Bank 3 are used to specify a
hold area instead of vertical masking. The FREEZE/RESUME
registers are used to define the hold area. The XV78HOLDEN
registers are used to specify whether XV7 and XV8 will use the
hold area or not.
Table 14. Vertical Sequence Registers (See Table 10 and Table 11 for the HBLK, CLPOB, and PBLK registers)
Register
Length Range
Description
VPATSEL
4b
0 to 9 Vertical Pattern Group No. Selected Vertical Pattern Group for Each Vertical Sequence.
VMASK
2b
0 to 3 Mask Mode
Enables the Masking of V1 to V6 Outputs at the Locations Specified by the
FREEZE/RESUME Registers.
0 = No Mask.
1 = Enable Freeze1/Resume1.
2 = Enable Freeze2/Resume2.
3 = Enable Both 1 and 2.
VPATREPO
12 b 0 to 4095 Number of Repeats
Number of Repetitions for the Vertical Pattern Group for Odd Lines. If no
odd/even alternation is required, set equal to VPATREPE.
VPATREPE
12 b 0 to 4095 Number of Repeats
Number of Repetitions for the Vertical Pattern Group for Even Lines. If no
odd/even alternation is required, set equal to VPATREPO.
VPATSTART 12 b 0 to 4095 Pixel Location
Start Position for the Selected Vertical Pattern Group.
HDLEN
13 b 0 to 8191 Number of Pixels
HD Line Length for Lines in Each Vertical Sequence. Note that 13^th bit (MSB)
of the line length is located in a separate register to maintain compatibility
with AD9995.
HOLD¹
1b
High/Low
Enable Hold Area Instead of Vertical Masking, Using FREEZE/RESUME
Registers.
XV78HOLDEN¹ 1 b
High/Low
Enable XV7 and XV8 to Use Hold Area.
0 = Disable.
1 = Enable.
1_{Located in Bank 3, vertical sequence registers for XV7 and XV8.}
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