ADSP-21065LKSZ-264 Datasheet, PDF (26/44 Pages) Analog Devices – DSP Microcomputer

ADSP-21065L
Three-State Timing—Bus Master, Bus Slave, HBR, SBTS
These specifications show how the memory interface is disabled (stops driving) or enabled (resumes driving) relative to CLKIN and
the SBTS pin. This timing is applicable to bus master transition cycles (BTC) and host transition cycles (HTC) as well as the SBTS pin.
Parameter
Timing Requirements:
t_STSCK
t_HTSCK
SBTS Setup Before CLKIN
SBTS Hold Before CLKIN
Min
7.0 + 8 DT
Max
1.0 + 8 DT
Unit
ns
ns
Switching Characteristics:
t_MIENA
t_MIENS
t_MIENHG
Address/Select Enable After CLKIN
Strobes Enable After CLKIN¹
HBG Enable After CLKIN
t_MITRA
t_MITRS
t_MITRHG
t_DATEN
t_DATTR
t_ACKEN
t_ACKTR
t_MTRHBG
t_MENHBG
Address/Select Disable After CLKIN
Strobes Disable After CLKIN¹
HBG Disable After CLKIN
Data Enable After CLKIN²
Data Disable After CLKIN²
ACK Enable After CLKIN²
ACK Disable After CLKIN²
Memory Interface Disable Before HBG Low³
Memory Interface Enable After HBG High³
1.0 – 2 DT
ns
–0.5 – 2 DT
ns
2.0 – 2 DT
ns
3.0 – 4 DT
ns
4.0 – 4 DT
ns
5.5 – 4 DT
ns
10.0 + 5 DT
ns
1.0 – 2 DT
7.0 – 2 DT
ns
7.5 + 4 DT
ns
1.0 – 2 DT
6.0 – 2 DT
ns
2.0 + 2 DT
ns
15.75 + DT
ns
NOTES
1_{Strobes = RD, WR, SW, DMAG.}
2_{In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.}
3_{Memory Interface = Address, RD, WR, MSx, SW, DMAGx, BMS (in EPROM boot mode).}
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REV. C