ADSP-21065LKSZ-264 Datasheet, PDF (1/44 Pages) Analog Devices – DSP Microcomputer

a
DSP Microcomputer
ADSP-21065L
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC^®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral
I²S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)
CORE PROCESSOR
INSTRUCTION
CACHE
32 ؋ 48 BIT
DAG1
DAG2
8 ؋ 4 ؋ 32 8 ؋ 4 ؋ 24
PROGRAM
SEQUENCER
24 PM ADDRESS BUS
32 DM ADDRESS BUS
BUS
CONNECT
(PX)
48 PM DATA BUS
40 DM DATA BUS
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
ADDR
DATA
IOA
IOD
17
48
JTAG ₇
TEST &
EMULATION
EXTERNAL
PORT
SDRAM
INTERFACE
24
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
32
DATA BUS
MUX
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 ؋ 40 BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS, TIMER
&
DATA BUFFERS
DMA
CONTROLLER
SPORT 0
SPORT 1
I/O PROCESSOR
Figure 1. Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
4
(2 Rx, 2Tx)
(I²S)
(2 Rx, 2Tx)
(I²S)
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
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