EVAL-AD5933EBZ Datasheet, PDF (25/32 Pages) Analog Devices – Evaluation Board for the 1 MSPS 12-Bit Impedance Converter Network Analyzer

Preliminary Technical Data
Frequently Asked Questions
About Measuring Lower Excitation Frequencies
Q: I want to analyze frequencies in the range between 1 kHz and
10 kHz using the AD5933 with a 16 MHz crystal. Will this work?
A: This is possible, but you will need to scale the system clock
by using an external clock divider. This reduces the sampling
frequency of the ADC to a value less than 1 MHz (fSAMPLING =
MCLK/16); however, the 1024 sample set will now span the
response signal being analyzed. Note that by scaling the system
clock, you reduce the maximum bandwidth of the sweep.
You can use an additional low power DDS part, such as the
AD9834 (see Figure 31), or an integer N divider, such as the
ADF4001 (see Figure 32), to divide down a system clock signal
before applying it to the external clock pin (MCLK) of the
AD5933.
VDD
AD9834*
MCLK
SCLK FSYNC SDA
IOUT
VDD
ADCMP601*
SCLK FSYNC SDA
ADuC7020*
SCL
SDA
MCLK
AD5933*
OSCILLATOR
I²C
INTERFACE
MAC
DDS CORE
(27 BITS)
ADC
(9 BITS)
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 31. Using an External AD9834 to Scale the System Clock
RSET
REFINA/B
ADF4001*
REFIN
MUXOUT
SCLK FSYNC SDA CE
SCLK FSYNC SDA CE
ADuC7020*
SCL
SDA
MCLK
AD5933*
OSCILLATOR
I²C
INTERFACE
MAC
DDS CORE
(27 BITS)
ADC
(9 BITS)
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 32. Using an External Integer Divider to Scale the System Clock
EVAL-AD5933EB
Q: I have scaled the system clock connected to the AD5933 to
allow an analysis of lower clock frequencies. Although I
established the lower frequency limit (see Table 7), my upper
excitation frequency is now limited. What is the reason for this
limitation?
Table 7. Experimental Lower Frequency Limits vs. MCLK
Frequency AD5933 Lower
Interval Frequency¹
Clock Frequency Applied
to MCLK Pin²
1
100 kHz to 5 kHz 16 MHz
2
5 kHz to 1 kHz
4 MHz
3
5 kHz to 300 Hz
2 MHz
4
300 Hz to 200 Hz 1 MHz
5
200 Hz to 100 Hz 250 kHz
6
100 Hz to 30 Hz
100 kHz
7
30 Hz to 20 Hz
50 kHz
8
20 Hz to 10 Hz
25 kHz
1 _{The lower frequency sweep limit is established by applying the divided clock}
signal to the MCLK pin of the AD5933, and then calibrating and remeasuring
a nominal impedance, Z , CALIBRATION for example, a 200 kΩ resistor over a 500 Hz
linear sweep from the programmed start frequency (I-V gain resistor setting
= Z , CALIBRATION for example, 200 kΩ, PGA = ×1, Δ frequency = 5 Hz, number of
points = 100). The lower frequency limit is established as the frequency at
which the DFT, and hence the impedance vs. frequency results, begins to
degrade and deviate from the expected value of the measured impedance,
Z , CALIBRATION for example, 200 kΩ.
2 _{TTL clock levels applied to the MCLK pin, with VIH = 2 V and VIL = 0.8 V.}
A: In measuring lower clock frequencies, the two main
tradeoffs are that the AD5933 takes longer to return the
impedance results due to the slower ADC conversion clock
speed and that the upper excitation limit is restricted.
For example, if the user has established that a scaled clock
frequency of 4 MHz must be applied to the external clock pin of
the AD5933 to correctly analyze a 3 kHz signal, the applied
system clock (external or internal oscillator) is divided by a
factor of 4 before being routed as the reference clock to the
DDS. The system clock is directly connected to the ADC
without further division so that the ADC sampling clock is
running at four times the speed of the DDS core. Therefore,
with a system clock of 4 MHz, the DDS reference clock is 1/4 ×
4 MHz = 1 MHz, and the ADC clock is 4 MHz. The AD5933
DDS has a 27-bit phase accumulator; however, the top three
most significant bits (MSBs) are internally connected to Logic
0. Therefore, with the top three MSBs set to 0, the maximum
DDS output frequency is further reduced by a factor of 1/8, and
the maximum output frequency is 1/32 × 1 MHz = 31.25 kHz.
Therefore, it is possible to accurately measure the 3 kHz signal
using a lower system clock of 4 MHz; however, the AD5933
takes longer to return the impedance results due to the slower
ADC conversion clock speed and the upper excitation limit is
now restricted to 31.25 KHz.
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