EVAL-AD5933EBZ Datasheet, PDF (24/32 Pages) Analog Devices – Evaluation Board for the 1 MSPS 12-Bit Impedance Converter Network Analyzer

EVAL-AD5933EB
system clock frequency of 16.776 MHz, the ADC can sample
the response signal with a frequency of 1.0485 MHz, that is, a
throughput rate of ≈1.04 MSPS. The ADC converts 1024 samples
and passes the digital results to the multiply accumulate (MAC)
core for processing. The AD5933 MAC core performs a 1024-
point DFT to determine the peak of the response signal at the
ADC input. The DFT offers many advantages over conventional
peak detection mechanisms, including excellent dc rejection as
well as an averaging of errors and phase information.
The throughput rate of the AD5933 ADC scales with the system
clock. Therefore, lower ADC throughput rates, and hence sampling
frequencies, can be achieved by lowering the system clock.
The conventional DFT assumes a sequence of periodic input
data samples in order to determine the spectral content of the
original continuous signal. In the AD5933, these samples come
from the 12-bit ADC for a user-defined range of signal
frequencies. The conventional DFT correlates the input signal
with a series of test phasor frequencies in order to determine
the fundamental signal frequency and its harmonics. The
frequency of the test phasor is at integer multiples of a
fundamental frequency given by the following formula:
Test Phasor Frequency = ^{f S}
N
where fS is the sampling frequency of ADC, and N is the
number of samples taken (1024).
The correlation is performed for each integer frequency. If the
resulting correlation of the test phasor with the input sample set
is nonzero, there is signal energy at this frequency. If no energy
is found in a bin, there is no energy at that test frequency.
The DFT implemented by the AD5933 is called a single-point
DFT, meaning that the analysis or correlation frequency in the
MAC core is always at the same frequency as the current output
excitation frequency. Therefore, when the system clock for the
Preliminary Technical Data
AD5933 is 16.776 MHz, the sample rate of the ADC is 1.04 MHz.
The DSP core requires 1024 samples to perform the single-point
DFT. Therefore, the resolution of the DFT is 1.04 MHz/1024 points
≈ 1 kHz. This calculation is based on a system clock frequency
of 16 MHz applied at MCLK. If the AD5933 tries to examine
excitation frequencies below ≈1 kHz, the errors introduced by
spectral leakage become very significant and result in erroneous
impedance readings.
If the input signal over the 1024-point sample interval is an
integer, there will be a smooth transition from the end of one
period to the beginning of the next point, as shown in Figure 29. If
this number is not an integer, there will not be a smooth
transition from the end of one period to the beginning of the
next point, as shown in Figure 30. The leakage is a result of the
discontinuities introduced by the DFT, assuming a periodic
input signal like that shown in Figure 30.
In order for the AD5933 to analyze the impedance (ZUNKNOWN)
at frequencies lower than ≈1 kHz, it is necessary to scale the
system clock so that the sample rate of the ADC is lower and
causes the 1024 samples required for the single-point DFT to
cover an integer number of periods of the current excitation
frequency.
SAMPLES SPAN ENTIRE EXCITATION PERIOD
SAMPLE DFT ASSUMES A PERIODIC
WINDOW
SAMPLE SET
Figure 29. Sample Set Spanning the Entire Excitation Period
SAMPLES DO NOT SPAN ENTIRE EXCITATION PERIOD
DFT ASSUMES A PERIODIC
SAMPLE SET
Figure 30. Sample Set not Spanning the Entire Excitation Period
Rev. PrC | Page 24 of 32