EVAL-AD5933EBZ Datasheet, PDF (23/32 Pages) Analog Devices – Evaluation Board for the 1 MSPS 12-Bit Impedance Converter Network Analyzer

Preliminary Technical Data
EVAL-AD5933EB
effect on the AD5933 calibration (that is, the gain factor
calculation) and subsequent impedance readings in comparison
with those obtained by connecting the small impedance directly
to the VOUT pin (and directly in series with ROUT). The
external amplifier buffers the unknown impedance from the
effects of the output series resistance of the AD5933 (ROUT) and
introduces a smaller output impedance in series with the
impedance being tested (ZUNKNOWN).
TRANSMIT SIDE
OUTPUT AMPLIFIER
2V p-p
DDS
ROUT VOUT
R2
V_DD
20kΩ
R_FB ^20kΩ
V_DD/2
1µF
R1
AD8531
AD820
AD8641
AD8627
R_FB
PGA
I-V
VIN
Z_UNKNOWN
V_DD/2
Figure 28. Additional External Amplifier Circuit
for Measuring Small Impedances
For example, a user might want to measure an impedance,
ZUNKNOWN, that is known to have a value within the range of 90 Ω
to 110 Ω (that is, a small impedance) over the frequency range
of 30 kHz to 32 kHz. In this case, the user may not be able to
characterize the output series resistance (ROUT) directly in the
factory/lab. Therefore, the user may choose to add an extra
amplifier circuit as shown in Figure 28 to the signal path of the
AD5933. The user must ensure that the chosen external
amplifier has a sufficiently low output series resistance over the
bandwidth of interest in comparison with the impedance range
being tested (visit www.analog.com/opamps for an op amp
selection guide). The data sheets of most Analog Devices
amplifiers show the closed loop output impedance vs. frequency
at different amplifier gains to provide an idea of the effect on
output series impedance.
The system settings are as follows:
VDD = 3.3 V
VOUT = 2 V p-p
R2 = 20 kΩ
R1 = 4 kΩ
Gain setting resistor = 500 Ω
ZUNKNOWN = 100 Ω
PGA setting = ×1
Choose a ratio of R1/R2 to attenuate the excitation voltage at VOUT.
With the values of R1 = 4 kΩ and R2 = 20 kΩ, the signal is attenu-
ated by 1⁄5 (1/5 of 2 V p-p = 400 mV). The maximum current
flowing through the impedance will be 400 mV/90 Ω = 4.4 mA.
The system is subsequently calibrated at a midpoint frequency
in the sweep using the usual method with a midpoint impedance
value of 100 Ω for the calibration resistor and feedback resistor.
Increasing the value of the I-V gain resistor at the RFB pin
improves the dynamic range of the input signal to the receive
side of the AD5933. For example, by increasing the I-V gain
setting resistor at the RFB pin, the peak-to-peak signal presented to
the ADC input increases from 400 mV (Rfb = 100 Ω) to 2 V p-p
(Rfb = 500 Ω).
The gain factor calculated is for a 100 Ω resistor connected
between VOUT and VIN, assuming the output series resistance
of the external amplifier is small enough to be ignored.
One final important point to note about the biasing of the
circuit shown in Figure 28 is that the receive side of the AD5933
is hard biased about VDD/2 by design. Therefore, to prevent the
output of the external amplifier (attenuated AD5933 range 1
excitation signal) from saturating the receive side amplifiers of
the AD5933, a voltage equal to VDD/2 must be applied to the
noninverting terminal of the external amplifier.
Measuring Lower Excitation Frequencies
The AD5933 has a flexible internal direct digital synthesizer (DDS)
core and DAC, which together generate the excitation signal
used to measure the impedance (ZUNKNOWN). The DDS core has a
27-bit phase accumulator, allowing subhertz (<0.1 Hz)
frequency resolution. The output of the phase accumulator is
connected to the input of a read only memory (ROM). The
digital output of the phase accumulator is used to address
individual memory locations in the ROM. The digital contents
of the ROM represent amplitude samples of a single cycle of a
sinusoidal excitation waveform. The content of each address
within the ROM look-up table are in turn passed to the input of
a digital-to-analog converter (DAC) that produces the analog
excitation waveform made available at the VOUT pin. The DDS
core (that is, the phase accumulator and the ROM look-up
table) and the DAC are referenced from a single system clock.
The function of the phase accumulator is to act as a system
clock divider.
The system clock for the AD5933 DDS engine can be provided
in one of two ways.
• Use a highly accurate and stable clock (crystal oscillator) at
the external clock pin (MCLK, Pin 8).
• Use the AD5933 internal clock oscillator with a typical
frequency of 16.776 MHz. (The internal oscillator is not
available in the AD5934; therefore, the user must apply a
clock to the external clock pin (MCLK).)
Select the preferred system clock by programming Bit D3 in the
CONTROL register (Address 81 hex; see AD5933 data sheet).
The system clock is also used by the internal ADC to digitize
the response signal. The ADC requires 16 clock periods to
perform a single conversion. Therefore, with a maximum
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