ADSP-BF533 Datasheet, PDF (25/60 Pages) Analog Devices – Blackfin Embedded Processor

Asynchronous Memory Read Cycle Timing
Table 17. Asynchronous Memory Read Cycle Timing
Parameter
Timing Requirements
t_SDAT
DATA15–0 Setup Before CLKOUT
t_HDAT
DATA15–0 Hold After CLKOUT
t_SARDY
ARDY Setup Before CLKOUT
t_HARDY
ARDY Hold After CLKOUT
Switching Characteristics
t_DO
Output Delay After CLKOUT¹
t_HO
Output Hold After CLKOUT ¹
1 _{Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, ARE.}
CLKOUT
AMSx
SETUP
2 CYCLES
t_DO
PROGRAMMED READ ACCESS
4 CYCLES
ADSP-BF533
V_DDEXT = 1.8 V
Min Max
V_DDEXT = 2.5 V/3.3 V
Min
Max
Unit
2.1
2.1
ns
1.0
0.8
ns
4.0
4.0
ns
1.0
0.0
ns
6.0
6.0
ns
1.0
0.8
ns
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t_HO
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA15–0
ABE, ADDRESS
t_DO
t_SARDY
t_HARDY
t_HO
t_HARDY
t_SARDY
t_SDAT
Figure 10. Asynchronous Memory Read Cycle Timing
READ
t_HDAT
Rev. D | Page 25 of 60 | September 2006