ADSP-BF533 Datasheet, PDF (13/60 Pages) Analog Devices – Blackfin Embedded Processor

where the variables in the equations are:
f_CCLKNOM is the nominal core clock frequency
f_CCLKRED is the reduced core clock frequency
V_DDINTNOM is the nominal internal supply voltage
V_DDINTRED is the reduced internal supply voltage
t_NOM is the duration running at f_CCLKNOM
t_RED is the duration running at f_CCLKRED
The percent power savings is calculated as:
% power savings = (1 – power savings factor) × 100%
VOLTAGE REGULATION
The Blackfin processors provide an on-chip voltage regulator
that can generate processor core voltage levels 0.85 V to 1.2 V
from an external 2.25 V to 3.6 V supply. Figure 5 shows the typ-
ical external components required to complete the power
management system.^† The regulator controls the internal logic
voltage levels and is programmable with the voltage regulator
control register (VR_CTL) in increments of 50 mV. To reduce
standby power consumption, the internal voltage regulator can
be programmed to remove power to the processor core while
keeping I/O power (V_DDEXT) supplied. While in hibernation,
V_DDEXT can still be applied, eliminating the need for external
buffers. The voltage regulator can be activated from this power-
down state either through an RTC wakeup or by asserting
RESET, which will then initiate a boot sequence. The regulator
can also be disabled and bypassed at the user’s discretion.
V_{DDEX T}
V_DDINT
100µF
10µH
2.25V TO 3.6V
INPUT VOLTAGE
RANGE
100µF 1µF
0.1µF
ZHCS1000
FDS9431A
VR_OUT1–0
EXTERNAL COMPONENTS
NOTE: VR_OUT1–0 SHOULD BE TIED TOGETHER EXTERNALLY
AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.
Figure 5. Voltage Regulator Circuit
CLOCK SIGNALS
The ADSP-BF533 processor can be clocked by an external crys-
tal, a sine wave input, or a buffered, shaped clock derived from
an external clock oscillator.
ADSP-BF533
If an external clock is used, it must not be halted, changed, or
operated below the specified frequency during normal opera-
tion. This signal is connected to the processor’s CLKIN pin.
When an external clock is used, the XTAL pin must be left
unconnected.
Alternatively, because the ADSP-BF533 processor includes an
on-chip oscillator circuit, an external crystal may be used. The
crystal should be connected across the CLKIN and XTAL pins,
with two capacitors connected as shown in Figure 6. Capacitor
values are dependent on crystal type and should be specified by
the crystal manufacturer. A parallel-resonant, fundamental fre-
quency, microprocessor-grade crystal should be used.
CLKIN
XTAL
CLKOUT
Figure 6. External Crystal Connections
As shown in Figure 7, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 0.5× to 64×
multiplication factor (bounded by specified minimum and max-
imum VCO frequencies). The default multiplier is 10×, but it
can be modified by a software instruction sequence. On-the-fly
frequency changes can be effected by simply writing to the
PLL_DIV register.
“FI NE” ADJUSTMENT
REQUI RES PLL SEQ UENCING
“CO ARSE” ADJUSTMENT
ON-THE -FLY
CLKI N
P LL
0.5× to 64×
VCO
÷ 1, 2, 4, 8
÷ 1 to 15
CCLK
SCLK
SCLK ≤ CCLK
SCLK ≤ 133 MHz
Figure 7. Frequency Modification Methods
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15. Table 6 illustrates typical system clock ratios.
† _{See EE-228: Switching Regulator Design Considerations for ADSP-BF533}
Blackfin Processors.
Rev. D | Page 13 of 60 | September 2006