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ADSP-21060C Datasheet, PDF (25/48 Pages) Analog Devices – ADSP-21060 Industrial SHARC DSP Microcomputer Family
ADSP-21060C/ADSP-21060LC
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership between
multiprocessing ADSP-2106xs (BRx) or a host processor
(HBR, HBG).
Parameter
Timing Requirements:
tHBGRCSV HBG Low to RD/WR/CS Valid1
tSHBRI HBR Setup before CLKIN2
tHHBRI HBR Hold before CLKIN2
tSHBGI HBG Setup before CLKIN
tHHBGI HBG Hold before CLKIN High
tSBRI BRx, CPA Setup before CLKIN3
tHBRI BRx, CPA Hold before CLKIN High
tSRPBAI RPBA Setup before CLKIN
tHRPBAI RPBA Hold before CLKIN
ADSP-21060C
Min
Max
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
20+ 5DT/4
14 + 3DT/4
6 + DT/2
6 + DT/2
12 + 3DT/4
ADSP-21060LC
Min
Max
Unit
20 + 3DT/4
13 + DT/2
13 + DT/2
21 + 3DT/4
20+ 5DT/4 ns
ns
14 + 3DT/4 ns
ns
6 + DT/2
ns
ns
6 + DT/2
ns
ns
12 + 3DT/4 ns
Switching Characteristics:
tDHBGO HBG Delay after CLKIN
tHHBGO HBG Hold after CLKIN
tDBRO BRx Delay after CLKIN
tHBRO BRx Hold after CLKIN
tDCPAO CPA Low Delay after CLKIN
tTRCPA CPA Disable after CLKIN
tDRDYCS REDY (O/D) or (A/D) Low from CS
and HBR Low4
tTRDYHG REDY (O/D) Disable or REDY (A/D)
High from HBG4
tARDYTR REDY (A/D) Disable from CS or
HBR High4
–2 – DT/8
–2 – DT/8
–2 – DT/8
40 + 23DT/16
7 – DT/8
7 – DT/8
8 – DT/8
4.5 – DT/8
8.5
10
–2 – DT/8
–2 – DT/8
–2 – DT/8
7 – DT/8
ns
ns
7 – DT/8
ns
ns
8.5 – DT/8 ns
4.5 – DT/8 ns
11.0
ns
40 + 23DT/16
ns
10
ns
NOTES
1For first asynchronous access after HBR and CS asserted, ADDR31-0 must be a non-MMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the “Host Processor Control of the ADSP-2106x” section in the
ADSP-2106x SHARC User’s Manual, Second Edition.
2Only required for recognition in the current cycle.
3CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.
4(O/D) = open drain, (A/D) = active drive.
REV. B
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