ADSP-21060C Datasheet, PDF (1/48 Pages) Analog Devices – ADSP-21060 Industrial SHARC DSP Microcomputer Family

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ADSP-21060 Industrial SHARC^®
DSP Microcomputer Family
ADSP-21060C/ADSP-21060LC
SUMMARY
High Performance Signal Processor for Communica-
tions, Graphics, and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch, and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
Industrial Temperature Grade Hermetic Ceramic QFP
Package
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced CQFP Package
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel
with Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
4 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
DAG1 DAG2
8 x 4 x 32 8 x 4 x 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS 32
BUS
CONNECT
(PX)
PM DATA BUS 48
DM DATA BUS 40/32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
IOD
IOA
48
17
JTAG ₇
TEST &
EMULATION
EXTERNAL
PORT
32
ADDR BUS
MUX
MULTIPROCESSOR
INTERFACE
48
DATA BUS
MUX
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
DMA
4
CONTROLLER
6
(MEMORY MAPPED)
SERIAL PORTS
(2)
6
CONTROL,
STATUS &
DATA BUFFERS
LINK PORTS
36
(6)
I/O PROCESSOR
Figure 1. Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
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© Analog Devices, Inc., 2001