ADSP-21060C Datasheet, PDF (18/48 Pages) Analog Devices – ADSP-21060 Industrial SHARC DSP Microcomputer Family

ADSP-21060C/ADSP-21060LC
Parameter
Clock Input
Timing Requirements:
t_CK
CLKIN Period
t_CKL
CLKIN Width Low
t_CKH
CLKIN Width High
t_CKRF
CLKIN Rise/Fall (0.4 V–2.0 V)
ADSP-21060C
40 MHz
33 MHz
Min Max Min Max
25
100 30
100
7
7
5
5
3
3
ADSP-21060LC
40 MHz
33 MHz
Min Max Min Max Unit
25
100 30
100 ns
9.5
9.5
ns
5
5
ns
3
3
ns
CLKIN
t_CK
t_CKH
t_CKL
Figure 8. Clock Input
Parameter
ADSP-21060C
Min
Max
ADSP-21060LC
Min
Max
Unit
Reset
Timing Requirements:
t_WRST
RESET Pulsewidth Low¹
4t_CK
4t_CK
ns
t_SRST
RESET Setup before CLKIN High²
14 + DT/2 t_CK
14 + DT/2 t_CK
ns
NOTES
1_{Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET}
is low, assuming stable V_DD and CLKIN (not including start-up time of external clock oscillator).
2_{Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required}
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
CLKIN
RESET
t_WRST
t_SRST
Figure 9. Reset
Parameter
Interrupts
Timing Requirements:
t_SIR
IRQ2-0 Setup before CLKIN High¹
t_HIR
IRQ2-0 Hold before CLKIN High¹
t_IPW
IRQ2-0 Pulsewidth²
NOTES
1_{Only required for IRQx recognition in the following cycle.}
2_{Applies only if tSIR and tHIR requirements are not met.}
ADSP-21060C
Min
Max
ADSP-21060LC
Min
Max
18 + 3DT/4
12 + 3DT/4
2 + t_CK
18 + 3DT/4
12 + 3DT/4
2 + t_CK
CLKIN
IRQ2-0
t_SIR
t_HIR
t_IPW
Figure 10. Interrupts
Unit
ns
ns
ns
–18–
REV. B