ADSP-TS101SAB1Z100 Datasheet, PDF (24/48 Pages) Analog Devices – TigerSHARC Embedded Processor

ADSP-TS101S
Table 25. Power-Up Reset Timing
Parameter
Min
Max
Timing Requirements
t_{START_LO}
RESET Deasserted After V_DD, V_{DD_A}, V_{DD_IO}, SCLK/LCLK, and 2
Static/Strap Pins Are Stable and Within Specification
t_{PULSE1_HI}
t_{PULSE2_LO}
t_{TRST_PWR1}
RESET Deasserted for First Pulse
RESET Asserted for Second Pulse
TRST Asserted During Power-Up Reset
50  t_SCLK
100  t_SCLK
2  t_SCLK
100  t_SCLK
1 _{Applies after VDD, VDD_A, VDD_IO, and SCLK/LCLK and static/strap pins are stable and within specification, and before RESET is deasserted.}
RESET
TRST
t_{START_LO}
t_{PULSE1_HI}
t_{PULSE2_LO}
t_{TRST_PW R}
V_DD, V_{DD_A,} V_{DD_IO,}
SCLK/LCLK,
S TAT IC /STR A P
PINS
Figure 14. Power-Up Reset Timing
Table 26. Normal Reset Timing
Parameter
Timing Requirements
t_{RST_IN}
t_STRAP
RESET Asserted
RESET Deasserted After Strap Pins Stable
Min
100  t_SCLK
2
RESET
STRAP PINS
t_{RST_IN}
t_{STRA P}
Max
Figure 15. Normal Reset (Hot Reset) Timing
Unit
ms
ns
ns
ns
Unit
ns
ms
Rev. C | Page 24 of 48 | May 2009