ADSP-TS101SAB1Z100 Datasheet, PDF (23/48 Pages) Analog Devices – TigerSHARC Embedded Processor

ADSP-TS101S
Table 22. Reference Clocks—System Clock (SCLK) Cycle Time
Parameter Description
t_SCLK1, ^{2, 3, 4}
System Clock Cycle Time
t_SCLKH
System Clock Cycle High Time
t_SCLKL
t_SCLKJ5, ⁶
System Clock Cycle Low Time
System Clock Jitter Tolerance
1 _{For more information, see Table 3 on Page 12.}
2 _{For more information, see Clock Domains on Page 9.}
3 _{LCLK_P and SCLK_P must be connected to the same source.}
4 _{The value of (tSCLK / LCLKRAT2-0) must not violate the specification for tCCLK.}
5 _{Actual input jitter should be combined with ac specifications for accurate timing analysis.}
6 _{Jitter specification is maximum peak-to-peak time interval error (TIE) jitter.}
Min
10
0.4 × t_SCLK
0.4 × t_SCLK
Max
25
0.6 × t_SCLK
0.6 × t_SCLK
500
Unit
ns
ns
ns
ps
SSCCLLKK__PP
tt_SSCCLLKK
tt_SSCCLLKKHH
t_SSCCLLKL
tt_SSCCLLKKJJ
Figure 11. Reference Clocks—System Clock (SCLK) Cycle Time
Table 23. Reference Clocks—Test Clock (TCK) Cycle Time
Parameter
t_TCK
t_TCKH
t_TCKL
Description
Test Clock (JTAG) Cycle Time
Test Clock (JTAG) Cycle High Time
Test Clock (JTAG) Cycle Low Time
Min
Greater of 30 or t_CCLK × 4
12.5
12.5
Max
t_TCK
t_TCKH
t_TCKL
TCK
Unit
ns
ns
ns
Figure 12. Reference Clocks—Test Clock (TCK) Cycle Time
Table 24. Power-Up Timing¹
Parameter
Min
Timing Requirement
t_{VDD_IO}
V_{DD_IO} Stable and Within Specification After V_DD and V_{DD_A} >0
Are Stable and Within Specification
1 _{For information about power supply sequencing and monitoring solutions, please visit http://www.analog.com/sequencing.}
Max
Unit
ms
V_DD
V_{DD_A}
V_{DD_IO}
t_{VDD_IO}
Figure 13. Power-Up Sequencing Timing
Rev. C | Page 23 of 48 | May 2009