AD9784_15 Datasheet, PDF (22/52 Pages) Analog Devices – 14-Bit, 200 MSPS/500 MSPS TxDAC

AD9784
Table 18.
CALMEMCK(OE)
CALMEM
CALCKDIV[2:0]
Table 19.
MEMRDWR(OF)
CALSTAT
CALEN
XFERSTAT
XFEREN
SMEMWR
SMEMRD
FMEMRD
UNCAL
Preliminary Technical Data
Bit
Direction
[5:4] O
[2:0] I
Default
00
00
Description
Calibration memory
00: Uncalibrated
01: Self Calibration
10: Factory calibration
11: User input
Calibration clock divide ratio from channel data rate
000: /32
001: /64
:
110: /2048
111: /4096
Bit Direction
7O
6I
5O
4I
3I
2I
1I
0I
Default
0
0
0
0
0
0
0
0
Description
0: Self Calibration cycle not complete
1: Self Calibration cycle complete
1: Self Calibration in progress
0: Factory memory transfer not complete
1: Factory memory transfer complete
1: Factory memory transfer in progress
1: Write static memory data from external port
1: Read static memory to external port
1: Read factory memory data to external port
1: Use uncalibrated
Table 20.
MEMADDR(10)
MEMADDR [7:0]
Bit
Direction
[7:0] I/O
Default
00000000
Description
Address of factory or static memory to be accessed
Table 21.
MEMDATA(11)
MEMDATA [5:0]
Bit
Direction
[5:0]
I/O
Default
000000
Description
Data or factory or static memory access
Table 22.
DCRCSTAT(12)
DCRCSTAT (2)
DCRCSTAT(1)
DCRCSTAT(0)
Bit Direction
2O
1O
0O
Default
0
0
0
Description
0: With DATACLK CRC on, lock has never been achieved
1: With DATACLK CRC on, lock has been achieved at least once
0: With DATACLK CRC on, system is currently not locked
1: With DATACLK CRC on, system is currently locked
0: With DATACLK CRC on, system is currently locked
1: With DATACLK CRC on, system lost lock due to jitter
Rev. PrC | Page 22 of 52