AD9784_15 Datasheet, PDF (1/52 Pages) Analog Devices – 14-Bit, 200 MSPS/500 MSPS TxDAC

Preliminary Technical Data
14-Bit, 200 MSPS/500 MSPS TxDAC+^® with
2×/4×/8× Interpolation and Signal Processing
AD9784
FEATURES
14-bit resolution, 200 MSPS input data rate
Selectable 2×/4×/8× interpolation filters
Selectable fDAC/2, fDAC/4, fDAC/8 modulation modes
Single or dual-channel signal processing
Selectable image rejection Hilbert transform
Flexible calibration engine
Direct IF transmission features
Serial control interface
Versatile clock and data interface
SFDR: 90 dBc @10 MHz
WCDMA ACLR = 80 dBc @ 40 MHz IF
DNL = ±0.75 LSB
INL = ±1.5 LSB
3.3 V compatible digital Interface
On-chip 1.2 V reference
80-lead thermally enhanced TQFP package
APPLICATIONS
Digital quadrature modulation architectures
Multicarrier WCDMA, GSM, TDMA, DCS,
PCS, CDMA Systems
PRODUCT DESCRIPTION
The AD9784 is a 14-bit, high speed, CMOS DAC with 2×/4×/8×
interpolation and signal processing features tuned for com-
munications applications. It offers state of the art distortion and
noise performance. The AD9784 was developed to meet the
demanding performance requirements of multicarrier and third
generation base stations. The selectable interpolation filters
simplify interfacing to a variety of input data rates while also
taking advantage of oversampling performance gains. The
modulation modes allow convenient bandwidth placement and
selectable sideband suppression.
The flexible clock interface accepts a variety of input types such
as 1 V p-p sine wave, CMOS, and LVPECL in single ended or
differential mode. Internal dividers generate the required data
rate interface clocks.
The AD9784 provides a differential current output, supporting
single-ended or differential applications; it provides a nominal
full-scale current from 10 mA to 20 mA. The AD9784 is
manufactured on an advanced low cost 0.25 µm CMOS process.
P1B[15:0]
P2B[15:0]
DATACLK/
PLL_LOCK
FUNCTIONAL BLOCK DIAGRAM
LATCH
×1
LATCH
2×
2×
2×
I
f_DAC/2
f_DAC/4
f_DAC/8
0
90
Q
2×
×2
2×
×4
2×
×8
0
90
0
90
∆t
ZERO
STUFF
16-BIT DAC
HILBERT
FSADJ
REFIO
I_OUTA
I_OUTB
SDIO
SDO
CSB
SCLK
RESET
CLK+
CLK–
LPF
CLOCK DISTRIBUTION AND CONTROL
Figure 1.
Rev. PrC
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