AD9601 Datasheet, PDF (22/32 Pages) Analog Devices – 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter

AD9601
Table 10. Serial Timing Definitions
Parameter
Timing (minimum, ns)
tDS
5
tDH
2
tCLK
40
tS
5
tH
2
tHI
16
tLO
16
tEN_SDIO
1
tDIS_SDIO
5
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 44)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 44)
Table 11. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< 0.62
= 0.62
=0
= 0.62
> 0.62 + 0.5 LSB
Offset Binary Output Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Twos Complement Mode
D11 to D0
0000 0000 0000
0000 0000 0000
0000 0000 0000
1111 1111 1111
1111 1111 1111
Gray Code Mode
(SPI Accessible)
D11 to D0
OR
0000 0000 0000
1
0000 0000 0000
0
0000 0000 0000
0
0000 0000 0000
0
0000 0000 0000
1
Rev. 0 | Page 22 of 32