AD9601 Datasheet, PDF (17/32 Pages) Analog Devices – 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter

CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9601 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally and require no additional bias.
Figure 36 shows one preferred method for clocking the AD9601.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9601 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9601 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
CLOCK
INPUT
0.1µF
MINI-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
XFMR
50Ω ^100Ω
0.1µF
CLK+
ADC
AD9601
CLK–
0.1µF
SCHOTTKY
DIODES:
HSM2812
Figure 36. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 37. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
CLOCK
INPUT
CLOCK
INPUT
50Ω*
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
CLK
0.1µF
PECL DRIVER
0.1µF
CLK
50Ω*
240Ω
100Ω
0.1µF
240Ω
CLK+
ADC
AD9601
CLK–
*50Ω RESISTORS ARE OPTIONAL.
Figure 37. Differential PECL Sample Clock
CLOCK
INPUT
CLOCK
INPUT
50Ω*
0.1µF
CLK
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
LVDS DRIVER
0.1µF
CLK
50Ω*
100Ω
0.1µF
CLK+
ADC
AD9601
CLK–
*50Ω RESISTORS ARE OPTIONAL.
Figure 38. Differential LVDS Sample Clock
AD9601
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 39). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
CLOCK
INPUT
0.1µF
50Ω*
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω ^0.1µF
CLK+
ADC
AD9601
0.1µF
39kΩ
CLK–
*50Ω RESISTOR IS OPTIONAL.
Figure 39. Single-Ended 1.8 V CMOS Sample Clock
CLOCK
INPUT
0.1µF
50Ω*
0.1µF
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
CLK
CMOS DRIVER
CLK
OPTIONAL
100Ω
0.1µF
CLK+
ADC
AD9601
0.1µF
CLK–
*50Ω RESISTOR IS OPTIONAL.
Figure 40. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance
is required on the clock duty cycle to maintain dynamic per-
formance characteristics. The AD9601 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling edge, providing
an internal clock signal with a nominal 50% duty cycle. This
allows a wide range of clock input duty cycles without affecting
the performance of the AD9601. When the DCS is on, noise
and distortion performance are nearly flat for a wide range of
duty cycles. However, some applications may require the DCS
function to be off. If so, keep in mind that the dynamic range
performance can be affected when operated in this mode. See the
AD9601 Configuration Using the SPI section for more details
on using this feature.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
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