AD9601 Datasheet, PDF (1/32 Pages) Analog Devices – 10-Bit, 200 MSPS/250 MSPS 1.8 V Analog-to-Digital Converter

FEATURES
SNR = 59.4 dBFS @ fIN up to 70 MHz @ 250 MSPS
ENOB of 9.7 @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
SFDR = 81 dBc @ fIN up to 70 MHz @ 250 MSPS (−1.0 dBFS)
Excellent linearity
DNL = 0.2 LSB typical
INL = 0.2 LSB typical
CMOS outputs
Single data port at up to 250 MHz
Demultiplexed dual port at up to 2 × 125 MHz
700 MHz full power analog bandwidth
On-chip reference, no external decoupling required
Integrated input buffer and track-and-hold
Low power dissipation
274 mW @ 200 MSPS
322 mW @ 250 MSPS
Programmable input voltage range
1.0 V to 1.5 V, 1.25 V nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data capture clock
10-Bit, 200 MSPS/250 MSPS
1.8 V Analog-to-Digital Converter
AD9601
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
FUNCTIONAL BLOCK DIAGRAM
RBIAS PWDN
AGND
AVDD (1.8V)
CML
VIN+
VIN–
CLK+
CLK–
REFERENCE
AD9601
TRACK-AND-HOLD
CLOCK
MANAGEMENT
ADC 10
10-BIT
CORE
SERIAL PORT
OUTPUT 10
STAGING
LVDS
RESET SCLK SDIO CSB
Figure 1.
DRVDD
DRGND
Dx9 TO Dx0
OVRA
OVRB
DCO+
DCO–
GENERAL DESCRIPTION
The AD9601 is a 10-bit monolithic sampling analog-to-digital
converter optimized for high performance, low power, and ease
of use. The product operates at up to a 250 MSPS conversion
rate and is optimized for outstanding dynamic performance in
wideband carrier and broadband systems. All necessary func-
tions, including a track-and-hold (T/H) and voltage reference,
are included on the chip to provide a complete signal
conversion solution.
The ADC requires a 1.8 V analog voltage supply and a differen-
tial clock for full performance operation. The digital outputs are
CMOS compatible and support either twos complement, offset
binary format, or Gray code. A data clock output is available for
proper output data timing.
Fabricated on an advanced CMOS process, the AD9601 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Performance—Maintains 59.4 dBFS SNR @ 250 MSPS
with a 70 MHz input.
2. Low Power—Consumes only 322 mW @ 250 MSPS.
3. Ease of Use—CMOS output data and output clock signal
allow interface to current FPGA technology. The on-chip
reference and sample-and-hold provide flexibility in
system design. Use of a single 1.8 V supply simplifies
system power supply design.
4. Serial Port Control—Standard serial port interface supports
various product functions, such as data formatting, power-
down, gain adjust, and output test pattern generation.
5. Pin-Compatible Family—12-bit pin-compatible family
offered as the AD9626.
Rev. 0
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