ADSST-SHARC-MEL-100_15 Datasheet, PDF (20/28 Pages) Analog Devices – SHARC Mel-100 Audio Processor

ADSST-SHARC-Mel-100
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
Rating
Internal (Core) Supply Voltage (VDDINT)
Analog (PLL) Supply Voltage (AVDD)
External (I/O) Supply Voltage (VDDEXT)
Input Voltage
Output Voltage Swing
Load Capacitance
–0.3 V to +2.2 V
–0.3 V to +2.2 V
–0.3 V to +4.6 V
–0.5 V to VDDEXT + 0.5 V
–0.5 V to VDDEXT + 0.5 V
200 pF
Storage Temperature Range
–65°C to +150°C
Stresses greater than those listed above may cause permanent
damage to the device. These are stress ratings only; functional
operation of the device at these or any other conditions greater
than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
TIMING SPECIFICATIONS
The SHARC Mel-100 processor’s internal clock switches at
higher frequencies than the system input clock (CLKIN). To
generate the internal clock, the processor uses an internal
phase-locked loop (PLL). This PLL based clocking minimizes
the skew between the system clock (CLKIN) signal and the
processor’s internal clock (the clock source for the external port
logic and I/O pads).
The SHARC Mel-100 processor’s internal clock (a multiple of
CLKIN) provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access mode).
During reset, program the ratio between the processor’s internal
clock frequency and external (CLKIN) clock frequency with the
CLK_CFG1–0 and CLKDBL pins. Even though the internal
clock is the clock source for the external port, it behaves as
described on the Clock Rate Ratio chart in CLKDBL pin
description in Table 2. To determine switching frequencies for
the serial and link ports, divide down the internal clock using
the programmable divider control of each port (DIVx for the
serial ports and LxCLKD for the link ports).
CLKIN
(4.2MHz–50MHz)
XTAL
QUARTZ
CRYSTAL OR
CRYSTAL
OSCILLATOR
CLOCK
DOUBLER
×1, ×2
EP:
MULTIPROCESSING
HOST
SRAM
CLKOUT
PLLICLK
SBSRAM
(8.4MHz–50MHz)
LINK PORT:
×1, ×1/2, ×1/3,
CCLK
(33.3MHz
×1/4 BY SW
LCLK[1:0]
TO 100MHz)
RATIOS
×2, ×3, ×4
CORE
IO-PROCESSOR
PLL
EP:
SDRAM
×1/2, ×1 BY SW SDCLK[1:0]
CLKDBL
CLK_CFG[1:0]
Figure 13. Core Clock and System Relationship to CLKIN
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