ADSST-SHARC-MEL-100_15 Datasheet, PDF (17/28 Pages) Analog Devices – SHARC Mel-100 Audio Processor

SPICLK
SPIDS
TCK
TDI
TDO
TIMEXP
TMS
TRST
VDDINT
VDDEXT
WR
XTAL
I/O
I
I
I/S
O
O
I/S
I/A
P
P
I/O/T
O
ADSST-SHARC-Mel-100
Serial Peripheral Interface Clock Signal. Driven by the master, this signal controls the rate at which data is
transferred. The master may transmit data at a variety of baud rates.
SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during data transfers, only
for the length of the transferred word. Slave devices ignore the serial clock if the slave select input is driven
inactive (high). SPICLK is used to shift out and shift in the data driven on the MISO and MOSI lines. The data is
always shifted out on one clock edge of the clock and sampled on the opposite edge of the clock. Clock
polarity and clock phase relative to data are programmable into the SPICTL control register and define the
transfer format. SPICLK has an internal pull-up resistor.
Serial Peripheral Interface Slave Device Select. An active low signal used to enable slave devices. This
input signal behaves like a chip select, and is provided by the master device for the slave devices. In
multimaster mode, the SPIDS signal can be asserted to a master device to signal that an error has occurred
because some other device is also trying to be the master device. If asserted low when the device is in master
mode, it is considered a multimaster error. For a single-master, multiple-slave configuration where FLAG3–0
are used, this pin must be tied or pulled high to VDDEXT on the master device. For SHARC Mel-100 to SHARC
Mel-100 SPI interaction, any of the master SHARC Mel-100 processors’ FLAG3–0 pins can be used to drive the
SPIDS signal on the SHARC Mel-100 SPI slave device.
Test Clock (JTAG). Provides a clock for JTAG boundary scan.
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a 20 kΩ internal pull-up
resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan path.
Timer Expired. Asserted for four core clock cycles when the timer is enabled.
Test Mode Select (JTAG). Used to control the test state machine. TMS has a 20 kΩ internal pull-up resistor.
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed low) After power-up or held
low for proper operation of the SHARC Mel-100. TRST has a 20 kΩ internal pull-up resistor.
Core Power Supply. Nominally 1.8 V dc and supplies the DSP’s core processor (14 pins).
I/O Power Supply. Nominally 3.3 V dc (13 pins).
Memory Write Low Strobe. WR is asserted when the SHARC Mel-100 writes a word to external memory or
IOP registers of other SHARC Mel-100 processors. External devices must assert WR for writing to the SHARC
Mel-100’s IOP registers. In a multiprocessing system, WR is driven by the bus master. WR has a 20 kΩ internal
pull-up resistor that is enabled for DSPs with ID2–0 = 00x.
Crystal Oscillator Terminal 2. Used in conjunction with CLKIN to enable the SHARC Mel-100’s internal clock
oscillator or to disable it to use an external clock source. See CLKIN.
BOOT MODES
Table 3. Boot Mode Selection
EBOOT
LBOOT
BMS
1
0
Output
0
0
1 (Input)
0
1
0 (Input)
0
1
1 (Input)
0
0
0 (Input)
1
1
x (Input)
Booting Mode
EPROM (Connect BMS to EPROM chip select).
Host Processor.
Serial Boot via SPI.
Link Port.
No Booting. Processor executes from external memory.
Reserved.
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